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IMX93CEC bảng dữ liệu(PDF) 61 Page - NXP Semiconductors

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• 802.1Qbu Frame preemption
• Time based Scheduling
• 1.8 V/3.3 V RMII operation, 1.8 V RGMII operation
4.12.3.1 Ethernet QOS signal mapping
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints
for the physical interface.
Table 65. ENET QOS signal mapping[1]
Pad name
RGMII
Alt mode
RMII
Alt mode
Direction
ENET1_MDC
RGMII_MDC
Alt 0
RMII_MDC
Alt 0
O
ENET1_MDIO
RGMII_MDIO
Alt 0
RMII_MDIO
Alt 0
I/O
ENET1_TXC
RGMII_TXC
Alt 0
RMII_TX_ER
Alt 1
O
ENET1_TX_CTL
RGMII_TX_CTL
Alt 0
RMII_TX_EN
Alt 0
O
ENET1_TD0
RGMII_TD0
Alt 0
RMII_TD0
Alt 0
O
ENET1_TD1
RGMII_TD1
Alt 0
RMII_TD1
Alt 0
O
ENET1_TD2
RGMII_TD2
Alt 0
RMII_REF_CLK[2]
Alt 1
I/O
ENET1_TD3
RGMII_TD3
Alt 0
—
Alt 0
O
ENET1_RXC
RGMII_RXC
Alt 0
RMII_RX_ER
Alt 1
I
ENET1_RX_CTL
RGMII_RX_CTL
Alt 0
RMII_CRS_DV
Alt 0
I
ENET1_RD0
RGMII_RD0
Alt 0
RMII_RD0
Alt 0
I
ENET1_RD1
RGMII_RD1
Alt 0
RMII_RD1
Alt 0
I
ENET1_RD2
RGMII_RD2
Alt 0
—
Alt 0
I
ENET1_RD3
RGMII_RD3
Alt 0
—
Alt 0
I
[1] ENET1 is Ethernet QoS with TSN, while ENET2 is Ethernet MAC.
[2] The signal can be either input or output.
4.12.3.2 RMII mode timing
In RMII mode, enet1.RMII_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock.
Figure 31 shows RMII mode timings. Table 66 describes the timing parameters (M16–M21) shown in the figure.
NXP Semiconductors
IMX93CEC
i.MX 93 Applications Processors Data Sheet for Commercial Products
IMX93CEC
All information provided in this document is subject to legal disclaimers.
© 2026 NXP B.V. All rights reserved.
Product data sheet
Rev. 7 — 12 February 2026
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