IMX93CEC datasheet(63/123 Pages) NXP

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ENET_MDC (output)

ENET_MDIO (output)

M14

M15

M10

M11

M12

M13

ENET_MDIO (input)

Figure 32. MII serial management channel timing diagram

Table 67. MII serial management channel timing[1],[2],[3]

Characteristic

Min.

Max.

Unit

M10

ENET_MDC falling edge to ENET_MDIO output invalid (min.

propagation delay)

-1.5

—

M11

ENET_MDC falling edge to ENET_MDIO output valid (max.

propagation delay)

—

M12

ENET_MDIO (input) to ENET_MDC rising edge setup

—

M13

ENET_MDIO (input) to ENET_MDC rising edge hold

—

M14

ENET_MDC pulse width high

40%

60%

ENET_MDC period

M15

ENET_MDC pulse width low

40%

60%

ENET_MDC period

[1] The timings assume the following configuration: DSE[5:0] = 001111 and FSEL1[1:0] = 11.

[2] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

[3] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm. Unterminated, 5-inch microstrip trace

on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line should be equal to the selected

RDSON of the I/O pad output driver.

4.12.3.4 RGMII signal switching specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver devices.

Table 68. RGMII signal switching specifications[1],[2],[3],[4]

Symbol

Description

Min.

Max.

Unit

Tcyc

Clock cycle duration

7.2

8.8

TskewT

Data to clock output skew at transmitter

-500

500

TskewR

Data to clock input skew at receiver

2.6

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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