IMX93CEC datasheet(34/123 Pages) NXP

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Note: WDOGx_B output signals (for each one of the Watchdog modules) do not have dedicated pins, but are muxed out

through the IOMUX. See the IOMUXC chapter of the i.MX 93 Applications Processor Reference Manual (IMX93RM) for

detailed information.

4.8.3 JTAG timing parameters

Figure 10 depicts the JTAG test clock input timing. Figure 11 depicts the JTAG boundary scan timing. Figure 12 depicts the JTAG

test access port. Signal parameters are listed in Table 32.

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

JTAG_TCK

(Input)

VIH

VIL

SJ1

SJ2

SJ3

Figure 10. Test Clock Input Timing Diagram

JTAG_TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

Data

Outputs

VIH

VIL

Input Data Valid

Output Data Valid

SJ4

SJ5

SJ6

SJ7

SJ6

Figure 11. Boundary system (JTAG) timing diagram

JTAG_TCK

(Input)

JTAG_TDI

(Input)

JTAG_TDO

(Output)

JTAG_TDO

(Output)

JTAG_TDO

(Output)

VIH

VIL

Input Data Valid

Output Data Valid

JTAG_TMS

SJ8

SJ9

SJ10

SJ11

SJ10

SJ14

Figure 12. Test Access Port Timing Diagram

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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