IMX93CEC datasheet(10/123 Pages) NXP

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System Clock

Main CPU

Low Power Real Time Domain

External DRAM

32 kB I-cache

NEON

64 kB L2 Cache

FPU

32 kB D-cache

Performance Acceleration and IO Domain

Oscillator

DMA

Watchdog, Periodic Timer

Timer/PWM x2, Timer x2

Temperature Sensor

PLLs

256 kB L3 Cache (ECC)

Arm Cortex-M33

16 kB+16 kB Code+Sys Cache

FPU

MPU

NVIC

256 kB TCM/OCRAM w/ECC

LPUART x2, SPI x2

I2C x2, I3C

CAN-FD

2-lane I2S TDM Tx/Rx

8-ch PDM Mic Input

MQS

x16 LPDDR4/4X (Inline ECC)

Crypto

Tamper Detection

Secure Clock

Secure Boot

eFuse Key Storage

Random Number

LPUART x6, SPI x6

I2C x6, I3C

CAN-FD

FlexIO x2

ADC (4-channel, 12-bit)

2x Gigabit Ethernet (1 w/TSN)

2x USB 2.0

5-lane I

2S TDM Tx/Rx, SPDIF

8 bpp Parallel YUV/RGB Camera

Parallel RGB Display

PXP with 2D Graphics

High-efficiency NPU

MIPI-CSI 2-lane w/PHY

MIPI-DSI 4-lane w/PHY

4-lane LVDS w/PHY

DMA

Watchdog x3, Periodic Timer

Timer/PWM x2, Timer x2

Secure JTAG

3x SD/SDIO 3.0/eMMC 5.1

Octal SPI FLASH w/Inline Crypto

640 kB OCRAM w/ECC

EdgeLock Secure Enclave

2x Cortex-A55

System Control

Low Power Security MCU

Connectivity and I/O

ML and Multimedia

System Control

Memory

Figure 2. i.MX 93 system block diagram

3 Special signal considerations

Table 3 lists special signal considerations for the i.MX 93 processors. The signal names are listed in alphabetical order.

The package contact assignments can be found in Package information and contact assignments. Signal descriptions are

provided in the

i.MX 93 Reference Manual (IMX93RM).

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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