IMX93CEC datasheet(3/123 Pages) NXP

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Table 1. Features ...continued

Subsystem

Features

• Two-way set-associative 16 KB System Cache with parity support

• Two-way set-associative 16 KB Code Cache with parity support

• 256 KB tightly coupled memory (TCM)

Neural Processing Unit (NPU)

Neural Network performance (256 MACs operating up to 1.0 GHz and 2 OPS/MAC)

• NPU targets 8-bit and 16-bit integer RNN

• Handles 8-bit weights

Image Sensor Interface (ISI)

• Standard pixel formats commonly used in many camera input protocols

• Programmable resolutions up to 2K

• Image processing for:

— Supports one source of up to 2K horizontal resolution

— Supports pixel rate up to 200 Mpixel/s

• Image down scaling via decimation and bi-phase filtering

• Color space conversion

• Interlaced to progressive conversions

On-chip memory

Boot ROM (256 KB) for Cortex®-A55

Boot ROM (256 KB) for Cortex®-M33

On-chip RAM (640 KB)

External memory interface

16-bit DRAM interface:

• LPDDR4X/LPDDR4 with inline ECC

• Supports up to 2 Gbyte DDR memory space

Three Ultra Secure Digital Host Controller (uSDHC) interfaces:

• One eMMC 5.1 (8-bit) compliance with HS400 DDR signaling to support up to 400

MB/sec

• One SDXC (4-bit, no eMMC5.1, with extended capacity)

• One SDIO (4-bit, SD/SDIO 3.01 compliance with 200 MHz SDR signaling and up

to 100 MB/sec)

FlexSPI Flash with support for XIP (for Cortex®-A55 in low-power mode) and support

for either one Octal SPI or Quad SPI FLASH device. It also supports both Serial NOR

and Serial NAND flash using the FlexSPI.

Pixel Pipeline (PXP)

• BitBlit

• Flexible image composition options—alpha, chroma key

• Porter-Duff operation

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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