IMX93CEC datasheet(33/123 Pages) NXP

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[4] This value is dependent on Operating data rate.

[5] This is the maximum bit rate that defined by supported display types.

4.7 Differential I/O output buffer impedance

The Differential CCM interface is designed to be compatible with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits (2001) for details.

4.7.1 DDR I/O output impedance

DDR output driver and ODT impedances are controlled across PVT using ZQ calibration procedure with a 120 ohm ±1% resistor

to ground. Programmable drive strength and ODT impedance targets available in the NXP DDR tool are detailed in the device IBIS

model. Impedance deviation (calibration accuracy) is ±10% (Maximum/Minimum impedance) across PVT.

4.8 System modules timing

This section contains the timing and electrical parameters for the modules in each i.MX 93 processor.

4.8.1 Reset timing parameters

Figure 8 shows the reset timing and Table 30 lists the timing parameters.

POR_B

CC1

(Input)

Figure 8. Reset timing diagram

Table 30. Reset timing parameters

Parameter

Min Max

Unit

CC1

Duration of POR_B to be qualified as valid.

Note: POR_B rise/fall times must be 400 µs or less.

—

RTC_XTALI cycle

4.8.2 WDOG Reset timing parameters

Figure 9 shows the WDOG reset timing and Table 31 lists the timing parameters.

WDOGx_B

CC3

(Output)

Figure 9. WDOGx_B timing diagram

Table 31. WDOG

x_B timing parameters

Parameter

Min

Max

Unit

CC3

Duration of WDOG1_B Assertion

—

RTC_XTALI cycle

Note: RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or approximately 30 µs.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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