IMX93CEC datasheet(75/123 Pages) NXP

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Table 85. FlexSPI input timing in DDR mode where FlexSPI

n_MCR0[RXCLKSRC] = 0x1 (Low drive mode)

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation[1]

—

MHz

Setup time for incoming data

1.5

—

Hold time for incoming data

—

[1] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

F1 F2

FLEXSPI_SCLK

FLEXSPI_DATA[7:0]

Internal Sample Clocks

Figure 46. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

4.12.9.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

Note: In this mode, it is only working under 1.8 V.

Table 86. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Nominal and Overdrive mode)

[1]

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation

—

200

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-0.6

0.6

[1] These timing specifications are valid only for 1.8 V nominal I/O pad supply voltage.

Table 87. FlexSPI input timing in DDR mode where FlexSPI

n_MCR0[RXCLKSRC] = 0x3 (Low drive mode)

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation

—

133

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-0.9

0.9

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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