IMX93CEC datasheet(41/123 Pages) NXP

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LCDn_CLK

(falling edge capture)

LCDn_CLK

(rising edge capture)

LCDn_DATA[23:00]

LCDn Control Signals

Figure 14. LCD timing

Table 44. LCD timing parameters[1][2]

Parameter

Symbol

Min

Max

Unit

LCD pixel clock frequency[3]

tCLK(LCD)

—

MHz

LCD pixel clock high (falling edge capture)

tCLKH(LCD)

—

LCD pixel clock low (rising edge capture)

tCLKL(LCD)

—

LCD pixel clock high to data valid (falling edge capture)

td(CLKH-DV)

-1.5

1.5

LCD pixel clock low to data valid (rising edge capture)

td(CLKL-DV)

-1.5

1.5

LCD pixel clock high to control signal valid (falling edge capture)

td(CLKH-CTRLV)

-1.5

1.5

LCD pixel clock low to control signal valid (rising edge capture)

td(CLKL-CTRLV)

-1.5

1.5

[1] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm, unterminated, 5-inch microstrip trace

on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line should be equal to the selected

RDSON of the I/O pad output driver.

[2] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

[3] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

4.10 Audio

This section provides information about audio subsystem.

4.10.1 SAI switching specifications

This section provides the AC timings for the SAI in Controller (clocks driven) and Target (clocks input) modes. All timings are given

for non inverted serial clock polarity (SAI_TCR2[BCP] = 0, SAI_RCR2[BCP] = 0) and non inverted frame sync (SAI_TCR4[FSP]

= 0, SAI_RCR4[FSP] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by

inverting the clock signal (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

For the 50 MHz BCLK operation, the BCLK and SYNC must always be in the same direction as the data (source synchronous):

• SAI transmitter must be in asynchronous mode with BCLK and SYNC configuration as outputs

• SAI receiver must be:

— In asynchronous mode with BCLK and SYNC configuration as inputs

— In synchronous mode with SAI_RCR2[BCI] = 1

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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