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IMX93CEC bảng dữ liệu(PDF) 57 Page - NXP Semiconductors |
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IMX93CEC bảng dữ liệu(HTML) 57 Page - NXP Semiconductors |
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57 / 123 page ![]() • The maximum supported SDR frequency is 200 MHz which is covered in HS200 mode, and the maximum DDR frequency is 200 MHz as a part of HS400 mode. uSDHC3 supports up to SDR104 (200 MHz) on primary SD3_* pins, but when it is multiplexing on GPIO_IO[27:22], below are the modes supported: • eMMC High Speed DDR, High Speed SDR, and less than or equal to 26 MHz MMC legacy protocols are supported. • SDR50 (100 MHz) and SDR104 (200 MHz) modes are NOT supported. • eMMC HS400 and HS200 modes are NOT supported • The maximum supported SDR and DDR frequency is 50 and 52 MHz If IO is supplied by 3.3 V, the maximum supported SDR/DDR frequency is 50/52 MHz 4.12.2 Ethernet controller (ENET) AC electrical specifications Ethernet supports the following key features: • Support ENET AVB • Support IEEE 1588 • Support Energy Efficient Ethernet (EEE) • 1.8 V/3.3 V RMII operation, 1.8 V RGMII operation The following sections introduce the ENET AC electrical specifications. 4.12.2.1 ENET2 signal mapping The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 61. ENET2 signal mapping[1] Pad name RGMII Alt mode RMII Alt mode Direction ENET2_MDC RGMII_MDC Alt 0 RMII_MDC Alt 0 O ENET2_MDIO RGMII_MDIO Alt 0 RMII_MDIO Alt 0 I/O ENET2_TXC RGMII_TXC Alt 0 RMII_TX_ER Alt 1 O ENET2_TX_CTL RGMII_TX_CTL Alt 0 RMII_TX_EN Alt 0 O ENET2_TD0 RGMII_TD0 Alt 0 RMII_TD0 Alt 0 O ENET2_TD1 RGMII_TD1 Alt 0 RMII_TD1 Alt 0 O ENET2_TD2 RGMII_TD2 Alt 0 RMII_REF_CLK[2] Alt 1 I/O ENET2_TD3 RGMII_TD3 Alt 0 — Alt 0 O ENET2_RXC RGMII_RXC Alt 0 RMII_RX_ER Alt 1 I ENET2_RX_CTL RGMII_RX_CTL Alt 0 RMII_CRS_DV Alt 0 I ENET2_RD0 RGMII_RD0 Alt 0 RMII_RD0 Alt 0 I Table continues on the next page... NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 57 / 123 |
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