IMX93CEC datasheet(68/123 Pages) NXP

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Table 71. LPI2C module timing parameters[1] ...continued

Symbol

Description

Min

Max

Unit

Notes

Fast mode Plus (Fm+)

1000

High speed mode (Hs-mode) 0

3400

Ultra Fast mode (UFm)

5000

[1] For more details, see

UM10204 I2C-bus specification and user manual.

[2] Standard, Fast, Fast+, and Ultra Fast modes are supported; High speed mode (HS) in target mode.

4.12.6 Improved Inter-Integrated Circuit Interface (I3C) specifications

Unless otherwise specified, I3C specifications are timed to/from the VIH and/or VIL signal points.

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

4.12.6.1 I3C Push-Pull Timing Parameters for SDR Mode

I3C interface is not supported on GPIO-Standard-plus pad type for 5 V operation. Measurements are with maximum output load

of 30 pf, input transition of 1 ns.

Table 72. I3C Push-Pull Timing Parameters for SDR Mode

Symbol

Description

Min

Typ

Max

Unit

Condition

fSCL

SCL Clock Frequency

0.01

12.5

12.9

MHz

FSCL = 1 / (tDIG_L +

tDIG_H)

tDIG_L

SCL Clock Low Period [1][2]

—

tDIG_H

SCL Clock High Period [1]

—

tSCO

Clock in to Data Out for Slave [3]

[4]

—

tCR

SCL Clock Rise Time [5]

—

150e06 *

1 / fSCL

(capped

at 60)

—

tCF

SCL Clock Fall Time [5]

—

150e06 *

1 / fSCL

(capped

at 60)

—

tHD_PP

SDA Signal Data Hold in Push-

Pull Mode, Slave [6]

—

Applicable for slave

and master loopback

modes

tSU_PP

SDA Signal Data Setup in Push-

Pull Mode

—

N/A

Applicable for slave

and master loopback

modes.

[1] tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH (see Figure 30)

[2] As both edges are used, the hold time needs to be satisfied for the respective edges; i.e., tCF + 3 for falling edge clocks, and tCR + 3 for rising edge clocks.

[3] Devices with more than 12ns of tSCO delay shall set the limitation bit in the BCR, and shall support the GETMXDS CCC to allow the Master to read this value

and adjust computations accordingly. For purposes of system design and test conformance, this parameter should be considered together with pad delay, bus

capacitance, propagation delay, and clock triggering points.

[4] Pad delay based on 90 Ω / 4 mA driver and 50 pF load. Note that Master may be a Slave in a multi-Master system, and thus shall also adhere to this

requirement

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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