TMS320DM355CZCEA13 datasheet(115/163 Pages) TI1

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TMS320DM355

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SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for AEMIF Module (1) (2) (3) (see Figure 5-14 and Figure 5-15 ) (continued)

DM355

UNI

NO.

PARAMETER

MIN

Nom

MAX

Output setup time, EM_BA[1:0] valid to

tsu(EMBAV-EMOEL)

(RS)*E

EM_OE low

Output hold time, EM_OE high to

th(EMOEH-EMBAIV)

(RH)*E

EM_BA[1:0] invalid

Output setup time, EM_A[13:0] valid to

tsu(EMBAV-EMOEL)

(RS)*E

EM_OE low

Output hold time, EM_OE high to

th(EMOEH-EMAIV)

(RH)*E

EM_A[13:0] invalid

EM_OE active low width (EW = 0)

(RST)*E

tw(EMOEL)

EM_OE active low width (EW = 1)

(RST+(EWC*16))*E

td(EMWAITH-

Delay time from EM_WAIT deasserted to

EMOEH)

EM_OE high

READS (OneNAND Synchronous Burst Read)(4)

fc(EM_CLK)

Frequency, EM_CLK

tc(EM_CLK)

Cycle time, EM_CLK

1000

tsu(EM_ADVV-

Output setup time, EM_ADV valid before

EM_CLKH)

EM_CLK high

th(EM_CLKH-

Output hold time, EM_CLK high to EM_ADV

EM_ADVIV)

invalid

tsu(EM_AV-

Output setup time, EM_A[13:0]/EM_BA[1]

EM_CLKH)

valid before EM_CLK high

th(EM_CLKH-

Output hold time, EM_CLK high to

EM_AIV)

EM_A[13:0]/EM_BA[1] invalid

tw(EM_CLKH)

Pulse duration, EM_CLK high

tc(EM_CLK)/3

tw(EM_CLKL)

Pulse duration, EM_CLK low

tc(EM_CLK)/3

WRITES

EMIF write cycle time (EW = 0)

(WS+WST+WH)*E

tc(EMWCYCLE)

(WS+WST+WH+(EW

EMIF write cycle time (EW = 1)

C*16))*E

Output setup time, EM_CE[1:0] low to

(WS)*E

EM_WE low (SS = 0)

tsu(EMCEL-EMWEL)

Output setup time, EM_CE[1:0] low to

EM_WE low (SS = 1)

Output hold time, EM_WE high to

(WH)*E

EM_CE[1:0] high (SS = 0)

th(EMWEH-EMCEH)

Output hold time, EM_WE high to

EM_CE[1:0] high (SS = 1)

Output setup time, EM_BA[1:0] valid to

tsu(EMBAV-EMWEL)

(WS)*E

EM_WE low

Output hold time, EM_WE high to

th(EMWEH-EMBAIV)

(WH)*E

EM_BA[1:0] invalid

Output setup time, EM_A[13:0] valid to

tsu(EMAV-EMWEL)

(WS)*E

EM_WE low

Output hold time, EM_WE high to

th(EMWEH-EMAIV)

(WH)*E

EM_A[13:0] invalid

EM_WE active low width (EW = 0)

(WST)*E

tw(EMWEL)

EM_WE active low width (EW = 1)

(WST+(EWC*16))*E

td(EMWAITH-

Delay time from EM_WAIT deasserted to

EMWEH)

EM_WE high

(4)

During OneNAND Mode the EM_CLK is driven by 1/2 PLLC1SYSCLK2 clk.

DM355 Peripheral Information and Electrical Specifications

115

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