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TMS320DM355CZCEA13 bảng dữ liệu(PDF) 113 Page - Texas Instruments |
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TMS320DM355CZCEA13 bảng dữ liệu(HTML) 113 Page - Texas Instruments |
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113 / 163 page  TMS320DM355 www.ti.com SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010 5.7 External Memory Interface (EMIF) DM355 supports several memory and external device interfaces, including: • Asynchronous EMIF (AEMIF) for interfacing to SRAM. – OneNAND flash memories – NAND flash memories • DDR2/mDDR Memory Controller for interfacing to SDRAM. 5.7.1 Asynchronous EMIF (AEMIF) The EMIF supports the following features: • SRAM, etc. on up to 2 asynchronous chip selects addressable up to 64KB each • Supports 8-bit or 16-bit data bus widths • Programmable asynchronous cycle timings • Supports extended wait mode • Supports Select Strobe mode 5.7.1.1 NAND (NAND, SmartMedia, xD) The NAND features of the EMIF are as follows: • NAND flash on up to 2 asynchronous chip selects • 8 and 16-bit data bus widths • Programmable cycle timings • Performs 1-bit and 4-bit ECC calculation • NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory cards 5.7.1.2 OneNAND The OneNAND features supported are as follows. • NAND flash on up to 2 asynchronous chip selects • Only 16-bit data bus widths • Supports asynchronous writes and reads • Supports synchronous reads with continuous linear burst mode (Does not support synchronous reads with wrap burst modes) • Programmable cycle timings for each chip select in asynchronous mode Copyright © 2007–2010, Texas Instruments Incorporated DM355 Peripheral Information and Electrical Specifications 113 Submit Documentation Feedback Product Folder Link(s): TMS320DM355 |
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