MC9S08DZ96F2CLL datasheet(174/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

174

Freescale Semiconductor

8.3.4

MCG Status and Control Register (MCGSC)

654

210

LOLS

LOCK

PLLST

IREFST

CLKST

OSCINIT

FTRIM1

1 A value for FTRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM

mode, a default value of 0x0 is loaded.

Reset:

Figure 8-6. MCG Status and Control Register (MCGSC)

Table 8-6. MCG Status and Control Register Field Descriptions

Field

Description

LOLS

Loss of Lock Status — This bit is a sticky indication of lock status for the FLL or PLL. LOLS is set when lock

detection is enabled and after acquiring lock, the FLL or PLL output frequency has fallen outside the lock exit

frequency tolerance, Dunl. LOLIE determines whether an interrupt request is made when set. LOLS is cleared by

reset or by writing a logic 1 to LOLS when LOLS is set. Writing a logic 0 to LOLS has no effect.

0 FLL or PLL has not lost lock since LOLS was last cleared.

1 FLL or PLL has lost lock since LOLS was last cleared.

LOCK

Lock Status — Indicates whether the FLL or PLL has acquired lock. Lock detection is disabled when both the

FLL and PLL are disabled. If the lock status bit is set, changing the value of DMX32, DRS and IREFS bits in FBE,

FBI, FEE and FEI modes; DIV32 bit in FBE and FEE modes; TRIM[7:0] bits in FBI and FEI modes; RDIV[2:0]

bits in FBE, FEE, PBE and PEE modes; VDIV[3:0] bits in PBE and PEE modes; and PLLS bit, causes the lock

status bit to clear and stay clear until the FLL or PLL has reacquired lock. Entry into BLPI, BLPE or stop mode

also causes the lock status bit to clear and stay cleared until the exit of these modes and the FLL or PLL has

reacquired lock.

0 FLL or PLL is currently unlocked.

1 FLL or PLL is currently locked.

PLLST

PLL Select Status — The PLLST bit indicates the current source for the PLLS clock. The PLLST bit does not

update immediately after a write to the PLLS bit due to internal synchronization between clock domains.

0 Source of PLLS clock is FLL clock.

1 Source of PLLS clock is PLL clock.

IREFST

Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST

bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock

domains.

0 Source of reference clock is external reference clock (oscillator or external clock source as determined by the

EREFS bit in the MCGC2 register).

1 Source of reference clock is internal reference clock.

3:2

CLKST

Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits do not update

immediately after a write to the CLKS bits due to internal synchronization between clock domains.

Encoding 0 — Output of FLL is selected.

Encoding 1 — Internal reference clock is selected.

Encoding 2 — External reference clock is selected.

Encoding 3 — Output of PLL is selected.

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