MC9S08DZ96F2CLL datasheet(173/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

173

8.3.3

MCG Trim Register (MCGTRM)

654

210

TRIM1

1 A value for TRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM

mode, a default value of 0x80 is loaded.

Figure 8-5. MCG Trim Register (MCGTRM)

Table 8-5. MCG Trim Register Field Descriptions

Field

Description

7:0

TRIM

MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock

period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary

value in TRIM will increase the period, and decreasing the value will decrease the period.

An additional ﬁne trim bit is available in MCGSC as the FTRIM bit.

If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value

from the nonvolatile memory location to this register.

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