MC9S08DZ96F2CLL datasheet(170/458 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

170

Freescale Semiconductor

8.3

8.3.1

MCG Control Register 1 (MCGC1)

654

210

CLKS

RDIV

IREFS

IRCLKEN

IREFSTEN

Reset:

Figure 8-3. MCG Control Register 1 (MCGC1)

Table 8-1. MCG Control Register 1 Field Descriptions

Field

Description

7:6

CLKS

Clock Source Select — Selects the system clock source.

Encoding 0 — Output of FLL or PLL is selected.

Encoding 1 — Internal reference clock is selected.

Encoding 2 — External reference clock is selected.

Encoding 3 — Reserved, defaults to 00.

5:3

RDIV

External Reference Divider — Selects the amount to divide down the external reference clock. If the FLL is

selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected, the

resulting frequency must be in the range 1 MHz to 2 MHz. See Table 8-2 and Table 8-3 for the divide-by factors.

IREFS

Internal Reference Select — Selects the reference clock source.

1 Internal reference clock selected

0 External reference clock selected

IRCLKEN

Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK.

1 MCGIRCLK active

0 MCGIRCLK inactive

IREFSTEN

Internal Reference Stop Enable — Controls whether or not the internal reference clock remains enabled when

the MCG enters stop mode.

1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before

entering stop

0 Internal reference clock is disabled in stop

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