MC9S08DZ96F2CLL datasheet(276/458 Pages) FREESCALE

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

276

Freescale Semiconductor

Figure 12-23 shows the common 13-byte data structure of receive and transmit buffers for extended

identiﬁers. The mapping of standard identiﬁers into the IDR registers is shown in Figure 12-24.

All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1.

All reserved or unused bits of the receive and transmit buffers always read ‘x’.

Table 12-24. Message Buffer Organization

Offset

Address

Access

0x00X0

Identiﬁer Register 0

0x00X1

Identiﬁer Register 1

0x00X2

Identiﬁer Register 2

0x00X3

Identiﬁer Register 3

0x00X4

Data Segment Register 0

0x00X5

Data Segment Register 1

0x00X6

Data Segment Register 2

0x00X7

Data Segment Register 3

0x00X8

Data Segment Register 4

0x00X9

Data Segment Register 5

0x00XA

Data Segment Register 6

0x00XB

Data Segment Register 7

0x00XC

Data Length Register

0x00XD

Transmit Buffer Priority Register1

1 Not applicable for receive buffers

0x00XE

Time Stamp Register (High Byte)2

2 Read-only for CPU

0x00XF

Time Stamp Register (Low Byte)3

3 Read-only for CPU

1. Exception: The transmit priority registers are 0 out of reset.

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