MC9S08DZ96F2CLL datasheet(274/458 Pages) FREESCALE

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

274

Freescale Semiconductor

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

12.3.16 MSCAN Identiﬁer Mask Registers (CANIDMR0–CANIDMR7)

The identiﬁer mask register speciﬁes which of the corresponding bits in the identiﬁer acceptance register

are relevant for acceptance ﬁltering. To receive standard identiﬁers in 32 bit ﬁlter mode, it is required to

program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”

To receive standard identiﬁers in 16 bit ﬁlter mode, it is required to program the last three bits (AM[2:0])

in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 12-20. CANIDAR0–CANIDAR3 Register Field Descriptions

Field

Description

7:0

AC[7:0]

Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits

of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison

is then masked with the corresponding identiﬁer mask register.

76543210

AC7AC6

AC5AC4AC3AC2AC1AC0

Reset

00000000

Figure 12-20. MSCAN Identiﬁer Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7

Table 12-21. CANIDAR4–CANIDAR7 Register Field Descriptions

Field

Description

7:0

AC[7:0]

Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits

of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison

is then masked with the corresponding identiﬁer mask register.

76543210

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

Figure 12-21. MSCAN Identiﬁer Mask Registers (First Bank) — CANIDMR0–CANIDMR3

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