MC9S08DZ96F2CLL datasheet(273/458 Pages) FREESCALE

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

273

12.3.14 MSCAN Transmit Error Counter (CANTXERR)

This register reﬂects the status of the MSCAN transmit error counter.

Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and

INITAK = 1)

Write: Unimplemented

NOTE

Reading this register when in any other mode other than sleep or

initialization mode, may return an incorrect value. For MCUs with dual

CPUs, this may result in a CPU fault condition.

Writing to this register when in special modes can alter the MSCAN

functionality.

12.3.15 MSCAN Identiﬁer Acceptance Registers (CANIDAR0-7)

On reception, each message is written into the background receive buffer. The CPU is only signalled to

read the message if it passes the criteria in the identiﬁer acceptance and identiﬁer mask registers

(accepted); otherwise, the message is overwritten by the next message (dropped).

The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 12.4.1,

“Identiﬁer Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 12.5.3,

“Identiﬁer Acceptance Filter”).

For extended identiﬁers, all four acceptance and mask registers are applied. For standard identiﬁers, only

the ﬁrst two (CANIDAR0/1, CANIDMR0/1) are applied.

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

76543210

TXERR7

TXERR6

TXERR5

TXERR4

TXERR3

TXERR2

TXERR1

TXERR0

Reset:

00000000

= Unimplemented

Figure 12-18. MSCAN Transmit Error Counter (CANTXERR)

76543210

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

Figure 12-19. MSCAN Identiﬁer Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3

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