MC9S08DZ96F2CLL datasheet(278/458 Pages) FREESCALE

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

278

Freescale Semiconductor

Section 12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers, only

when RXF ﬂag is set (see Section 12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)”).

Write: For transmit buffers, anytime when TXEx ﬂag is set (see Section 12.3.6, “MSCAN Transmitter Flag

Section 12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for

receive buffers.

Reset: Undeﬁned (0x00XX) because of RAM-based implementation

12.4.1

Identiﬁer Registers (IDR0–IDR3)

The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits; ID[28:0], SRR, IDE,

and RTR bits. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits; ID[10:0],

RTR, and IDE bits.

12.4.1.1

IDR0–IDR3 for Extended Identiﬁer Mapping

Name

Bit 7

654321

Bit 0

IDR0

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

IDR1

ID2

ID1

ID0

RTR1

1 The position of RTR differs between extended and standard indentiﬁer mapping.

IDE2

2 IDE is 0.

IDR2

IDR3

= Unused, always read ‘x’

Figure 12-24. Receive/Transmit Message Buffer — Standard Identiﬁer Mapping

76543210

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

Reset:

xxxxxxxx

Figure 12-25. Identiﬁer Register 0 (IDR0) — Extended Identiﬁer Mapping

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