MC9S08DZ96F2CLL datasheet(248/458 Pages) FREESCALE

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Chapter 11 Inter-Integrated Circuit (S08IICV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

248

Freescale Semiconductor

11.4.3

General Call Address

General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches

the general call address as well as its own slave address. When the IIC responds to a general call, it acts as

a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after

the ﬁrst byte transfer to determine whether the address matches is its own slave address or a general call.

If the value is 00, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied

from a general call address by not issuing an acknowledgement.

11.5

Resets

The IIC is disabled after reset. The IIC cannot cause an MCU reset.

11.6

Interrupts

The IIC generates a single interrupt.

An interrupt from the IIC is generated when any of the events in Table 11-12 occur, provided the IICIE bit

is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC

control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. You

can determine the interrupt type by reading the status register.

11.6.1

Byte Transfer Interrupt

The TCF (transfer complete ﬂag) bit is set at the falling edge of the ninth clock to indicate the completion

of byte transfer.

11.6.2

Address Detect Interrupt

When the calling address matches the programmed slave address (IIC address register) or when the

GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is

interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.

11.6.3

Arbitration Lost Interrupt

The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more

masters try to control the bus at the same time, the relative priority of the contending masters is determined

by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration

process and the ARBL bit in the status register is set.

Table 11-12. Interrupt Summary

Interrupt Source

Status

Flag

Local Enable

Complete 1-byte transfer

TCF

IICIF

IICIE

Match of received calling address

IAAS

IICIF

IICIE

Arbitration Lost

ARBL

IICIF

IICIE

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