MC9S08DZ96F2CLL datasheet(246/458 Pages) FREESCALE

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Chapter 11 Inter-Integrated Circuit (S08IICV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

246

Freescale Semiconductor

the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set

by hardware to indicate loss of arbitration.

11.4.1.7

Clock Synchronization

Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all

the devices connected on the bus. The devices start counting their low period and after a device’s clock has

gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to

high in this device clock may not change the state of the SCL line if another device clock is still within its

low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.

Devices with shorter low periods enter a high wait state during this time (see Figure 11-10). When all

devices concerned have counted off their low period, the synchronized clock SCL line is released and

pulled high. There is then no difference between the device clocks and the state of the SCL line and all the

devices start counting their high periods. The ﬁrst device to complete its high period pulls the SCL line

low again.

Figure 11-10. IIC Clock Synchronization

11.4.1.8

Handshaking

The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold

the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces

the master clock into wait states until the slave releases the SCL line.

11.4.1.9

Clock Stretching

The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After

the master has driven SCL low the slave can drive SCL low for the required period and then release it. If

the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low

period is stretched.

SCL1

SCL2

SCL

Internal Counter Reset

Delay

Start Counting High Period

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