MC9S08DZ96F2CLL datasheet(247/458 Pages) FREESCALE

247 / 458 page

Chapter 11 Inter-Integrated Circuit (S08IICV2)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

247

11.4.2

10-bit Address

For 10-bit addressing, 0x11110 is used for the ﬁrst 5 bits of the ﬁrst address byte. Various combinations of

read/write formats are possible within a transfer that includes 10-bit addressing.

11.4.2.1

Master-Transmitter Addresses a Slave-Receiver

The transfer direction is not changed (see Table 11-10). When a 10-bit address follows a start condition,

each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own

address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match

and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the

second byte of the slave address with its own address. Only one slave finds a match and generates an

acknowledge (A2). The matching slave remains addressed by the master until it receives a stop condition

(P) or a repeated start condition (Sr) followed by a different slave address.

After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC

interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this

interrupt.

11.4.2.2

Master-Receiver Addresses a Slave-Transmitter

The transfer direction is changed after the second R/W bit (see Table 11-11). Up to and including

acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a

slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed

before. This slave then checks whether the ﬁrst seven bits of the ﬁrst byte of the slave address following

Sr are the same as they were after the start condition (S) and tests whether the eighth (R/W) bit is 1. If there

is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3.

The slave-transmitter remains addressed until it receives a stop condition (P) or a repeated start condition

(Sr) followed by a different slave address.

After a repeated start condition (Sr), all other slave devices also compare the ﬁrst seven bits of the ﬁrst byte

of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are

addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not

match.

After the master-receiver has sent the ﬁrst byte of the 10-bit address, the slave-transmitter sees an IIC

interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this

interrupt.

Slave Address 1st 7 bits

R/W

Slave Address 2nd byte

Data

...

Data

A/A

11110 + AD10 + AD9

AD[8:1]

Table 11-10. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address

Slave Address

1st 7 bits

R/W

Slave Address

2nd byte

Slave Address

1st 7 bits

R/W

Data

...

Data

11110 + AD10 + AD9

AD[8:1]

11110 + AD10 + AD9

Table 11-11. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address

MC9S08DZ96F2CLL bảng dữ liệu(PDF) 247 Page - Freescale Semiconductor, Inc

MC9S08DZ96F2CLL bảng dữ liệu(HTML) 247 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL