PSD4235G2V-10UI datasheet(40/100 Pages) STMICROELECTRONICS

40 / 100 page

PSD4256G6V

40/100

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

DECODE PLD (DPLD)

The DPLD, shown in Figure 13, is used for decod-

ing the address for internal and external compo-

nents. The DPLD can be used to generate the

following decode signals:

8 Sector Select (FS0-FS15) signals for the

primary Flash memory (three product terms

each)

4 Sector Select (CSBOOT0-CSBOOT3) signals

for the secondary Flash memory (three product

terms each)

1 internal SRAM Select (RS0) signal (three

product terms)

1 internal CSIOP Select (PSD Configuration

1 JTAG Select signal (enables JTAG-ISP on

Port E)

2 internal Peripheral Select signals (Peripheral

I/O mode).

Figure 13. DPLD Logic Array

Note: 1. The address inputs are A19-A4 when in 80C51XA mode

2. Additional address lines can be brought in the PSD via Port A, B, C, D, or F.

(INPUTS)

(32)

(8)

(16)

(1)

PDN (APD OUTPUT)

I /O PORTS (PORT A,B,C,F)

(8)

PGR0 - PGR7

(8)

MCELLA.FB [7:0] (FEEDBACKS)

MCELLB.FB [7:0] (FEEDBACKS)

A[15:0]

(4)

(3)

PD[3:0] (ALE,CLKIN,CSI)

CNTRL[2:0]

(READ/WRITE CONTROL SIGNALS)

(1)

RESET

RD_BSY

RS0

CSIOP

PSEL0

PSEL1

16 PRIMARY

FLASH

MEMORY

SECTOR

SELECTS

SRAM SELECT

I/O DECODER

SELECT

PERIPHERAL I/O

MODE SELECT

CSBOOT 0

CSBOOT 1

CSBOOT 2

CSBOOT 3

FS0

FS15

JTAGSEL

AI04925B

4 SECONDARY

FLASH

MEMORY

SECTOR

SELECTS

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