công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

PSD4235G2V-10UI bảng dữ liệu(PDF) 84 Page - STMicroelectronics

tên linh kiện PSD4235G2V-10UI
Giải thích chi tiết về linh kiện  Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
PDF  100 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD4235G2V-10UI bảng dữ liệu(HTML) 84 Page - STMicroelectronics

Back Button PSD4235G2V-10UI Datasheet HTML 80Page - STMicroelectronics PSD4235G2V-10UI Datasheet HTML 81Page - STMicroelectronics PSD4235G2V-10UI Datasheet HTML 82Page - STMicroelectronics PSD4235G2V-10UI Datasheet HTML 83Page - STMicroelectronics PSD4235G2V-10UI Datasheet HTML 84Page - STMicroelectronics PSD4235G2V-10UI Datasheet HTML 85Page - STMicroelectronics PSD4235G2V-10UI Datasheet HTML 86Page - STMicroelectronics PSD4235G2V-10UI Datasheet HTML 87Page - STMicroelectronics PSD4235G2V-10UI Datasheet HTML 88Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 84 / 100 page
background image
PSD4256G6V
84/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 39. Input to Output Disable / Enable
Table 61. CPLD Combinatorial Timing
Table 62. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. CLKIN (PD1) tCLCL = tCH + tCL.
Symbol
Parameter
Conditions
-10
PT
Aloc
Turbo
Off
Unit
Min
Max
tPD
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
38
+ 4
+ 20
ns
tEA
CPLD Input to CPLD Output
Enable
43
+ 20
ns
tER
CPLD Input to CPLD Output
Disable
43
+ 20
ns
tARP
CPLD Register Clear or
Preset Delay
38
+ 20
ns
tARPW
CPLD Register Clear or
Preset Pulse Width
28
+ 20
ns
tARD
CPLD Array Delay
Any
Macrocell
23
+ 4
ns
Symbol
Parameter
Conditions
-10
PT
Aloc
Turbo
Off
Unit
Min
Max
fMAX
Maximum Frequency
External Feedback
1/(tS+tCO)
22.7
MHz
Maximum Frequency
Internal Feedback (fCNT)
1/(tS+tCO–10)
29.4
MHz
Maximum Frequency
Pipelined Data
1/(tCH+tCL)
45.0
MHz
tS
Input Setup Time
18
+ 4
+ 20
ns
tH
Input Hold Time
0
ns
tCH
Clock High Time
Clock Input
11
ns
tCL
Clock Low Time
Clock Input
11
ns
tCO
Clock to Output Delay
Clock Input
26
ns
tARD
CPLD Array Delay
Any Macrocell
23
+ 4
ns
tMIN
Minimum Clock Period 1
tCH+tCL
22
ns
tER
tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com