PSD4235G2V-10UI datasheet(37/100 Pages) STMICROELECTRONICS

37 / 100 page

37/100

PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

PAGE REGISTER

The 8-bit Page Register increases the addressing

capability of the MCU by a factor of up to 256. The

contents of the register can also be read by the

MCU. The outputs of the Page Register (PGR0-

PGR7) are inputs to the DPLD decoder and can be

included

the

Sector

Select

(FS0-FS15,

CSBOOT0-CSBOOT3), and SRAM Select (RS0)

equations.

If memory paging is not needed, or if not all eight

page register bits are needed for memory paging,

these bits may be used in the CPLD for general

logic. See Application Note

AN1154.

Table 22, page 22 and Figure 11 show the Page

connected to the internal data bus (D0-D7). The

MCU can write to or read from the Page Register.

The Page Register can be accessed at address lo-

cation CSIOP + E0h.

Figure 11. Page Register

MEMORY ID REGISTERS

The 8-bit “Read only” Memory Status Registers

are included in the CSIOP space. The user can

determine the memory configuration of the PSD

device by reading the Memory ID0 and Memory

ID1 registers. The content of the registers is de-

fined as shown in Table 26, page 24 and Table 27,

page 24.

RESET

D 0-D 7

R/W

PAGE

PGR0

PGR1

PGR2

PGR3

DPLD

AND

CPLD

INTERNAL

SELECTS

AND LOGIC

PLD

PGR4

PGR5

PGR6

PGR7

AI02871B

PSD4235G2V-10UI bảng dữ liệu(PDF) 37 Page - STMicroelectronics

PSD4235G2V-10UI bảng dữ liệu(HTML) 37 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

bảng dữ liệu tải về

Link URL