PSD4235G2V-10UI datasheet(34/100 Pages) STMICROELECTRONICS

34 / 100 page

PSD4256G6V

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

SPECIFIC FEATURES

Flash Memory Sector Protect

Each sector of Primary or Secondary Flash mem-

ory can be separately protected against Program

and Erase cycles. Sector Protection provides ad-

ditional data security because it disables all Pro-

gram or Erase cycles. This mode can be activated

(or deactivated) through the JTAG-ISP Port or a

Device Programmer.

Sector protection can be selected for each sector

using the PSDsoft program. This automatically

protects selected sectors when the device is pro-

grammed through the JTAG Port or a Device Pro-

grammer.

Flash

memory

sectors

can

unprotected to allow updating of their contents us-

ing the JTAG Port or a Device Programmer. The

MCU can read (but cannot change) the sector pro-

tection bits.

Any attempt to program or erase a protected Flash

memory sector is ignored by the device. The Verify

operation results in a READ of the protected data.

This allows a guarantee of the retention of the Pro-

tection status.

The sector protection status can be read by the

MCU through the Flash memory protection and

Secondary Flash memory protection registers (in

the CSIOP block) or use the READ Sector Protec-

tion instruction. See Table 18, page 21 to Table

20, page 22.

RESET

The RESET instruction consists of one WRITE cy-

cle (see Table 29, page 27). It can also be option-

ally preceded by the standard two WRITE

decoding cycles (writing AAh to AAAh, and 55h to

554h).

The RESET instruction must be executed after:

– Reading the Flash Protection Status or Flash ID

– An Error condition has occurred (and the device

has set the Error Flag Bit (DQ5/DQ13) to '1')

during a Flash memory Program or Erase cycle.

The RESET instruction immediately puts the Flash

memory back into normal READ Mode. However,

if there is an error condition (with the Error Flag Bit

(DQ5/DQ13) set to '1') the Flash memory will re-

turn to the READ Mode in 25

µs after the RESET

instruction is issued.

The RESET instruction is ignored when it is issued

during a Program or Bulk Erase cycle of the Flash

memory. The RESET instruction aborts any on-

going Sector Erase cycle, and returns the Flash

memory to the normal READ Mode in 25

µs.

Reset (RESET) Pin

A pulse on the Reset (RESET) pin aborts any cy-

cle that is in progress, and resets the Flash mem-

ory to the READ Mode. When the reset occurs

during a Program or Erase cycle, the Flash mem-

ory takes up to 25

µs to return to the READ Mode.

It is recommended that the Reset (RESET) pulse

(except for Power On Reset, as described on page

74) be at least 25

µs so that the Flash memory is

always ready for the MCU to retrieve the bootstrap

instructions after the RESET cycle is complete.

SRAM

The SRAM is enabled when SRAM Select (RS0)

from the DPLD is High. SRAM Select (RS0) can

contain up to three product terms, allowing flexible

memory mapping.

The SRAM can be backed up using an external

battery. The external battery should be connected

to the Voltage Standby (VSTBY, PE6) line. If you

have an external battery connected to the PSD,

the contents of the SRAM are retained in the event

of a power loss. The contents of the SRAM are re-

tained so long as the battery voltage remains at 2V

or greater. If the supply voltage falls below the bat-

tery voltage, an internal power switch-over to the

battery occurs.

PE7 can be configured as an output that indicates

when power is being drawn from the external bat-

tery. This Battery-on Indicator (VBATON, PE7) sig-

nal is High when the supply voltage falls below the

battery voltage and the battery on Voltage Stand-

by (VSTBY, PE6) is supplying power to the internal

SRAM.

SRAM Select (RS0), Voltage Standby (VSTBY,

PE6) and Battery-on Indicator (VBATON, PE7) are

all configured using PSDsoft.

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