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PSD4235G2V-10UI bảng dữ liệu(PDF) 79 Page - STMicroelectronics |
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PSD4235G2V-10UI bảng dữ liệu(HTML) 79 Page - STMicroelectronics |
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79 / 100 page ![]() 79/100 PSD4256G6V This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Table 54. Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode Off) Conditions Highest Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 4 MHz % Flash memory Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 10% % Power-down Mode = 90% Number of product terms used (from fitter report) = 54 PT % of total product terms = 54/217 = 25% Turbo Mode = Off Calculation (using typical values) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE + %SRAM x 0.8 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50 µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz + 0.15 x 0.8 mA/MHz x 4 MHz + 15 mA) = 45 µA + 0.1 x (3.84 + 0.48 + 15) = 45 µA + 0.1 x 18.84 = 45 µA + 1.94 mA = 1.98 mA This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT = 0 mA. |
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