PSD4235G2V-10UI datasheet(26/100 Pages) STMICROELECTRONICS

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PSD4256G6V

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Primary Flash Memory and Secondary Flash memory Description

The primary Flash memory is divided evenly into 8

sectors. The secondary Flash memory is divided

into 4 sectors of different size. Each sector of ei-

ther memory block can be separately protected

from Program and Erase cycles.

Flash memory may be erased on a sector-by-sec-

tor basis, and programmed word-by-word. Flash

sector erasure may be suspended while data is

read from other sectors of the block and then re-

sumed after reading.

During a Program or Erase cycle in Flash memory,

the status can be output on the Ready/Busy pin

(PE4). This pin is set up using PSDsoft.

Memory Block Select Signals

The DPLD generates the Select signals for all the

internal memory blocks (see the section entitled

“PLDs”, on page 38). Each of the sectors of the pri-

mary Flash memory has a Select signal (FS0-

FS15) which can contain up to three product

terms. Each of the sectors of the secondary Flash

memory

has

Select

signal

(CSBOOT0-

CSBOOT3) which can contain up to three product

terms. Having three product terms for each Select

signal allows a given sector to be mapped in differ-

ent areas of system memory. When using a MCU

with

separate

Program

and

Data

space

(80C51XA), these flexible Select signals allow dy-

namic re-mapping of sectors from one memory

space to the other before and after IAP. The

SRAM block has a single Select signal (RS0).

Ready/Busy (PE4)

This signal can be used to output the Ready/Busy

status of the PSD. The output is a '0' (Busy) when

a Flash memory block is being written to,

or when

a Flash memory block is being erased. The output

is a '1' (Ready) when no WRITE or Erase cycle is

in progress.

Memory Operation

The primary Flash memory and secondary Flash

memory are addressed through the MCU Bus In-

terface. The MCU can access these memories in

one of two ways:

The MCU can execute a typical bus WRITE or

READ

operation just as it would if accessing a

RAM or ROM device using standard bus cycles.

The MCU can execute a specific instruction that

consists of several WRITE and READ

operations. This involves writing specific data

patterns to special addresses within the Flash

memory to invoke an embedded algorithm.

These instructions are summarized in Table 29,

page 27.

Typically, the MCU can read Flash memory using

READ operations, just as it would read a ROM de-

vice. However, Flash memory can only be erased

and programmed using specific instructions. For

example, the MCU cannot write a single byte di-

rectly to Flash memory as one would write a byte

to RAM. To program a word into Flash memory,

the MCU must execute a Program instruction, then

test the status of the Programming event. This sta-

tus test is achieved by a READ operation or polling

Ready/Busy (PE4).

Flash memory can also be read by using special

instructions to retrieve particular Flash device in-

formation (sector protect status and ID).

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