PSD4235G2V-10UI datasheet(68/100 Pages) STMICROELECTRONICS

68 / 100 page

PSD4256G6V

68/100

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Port E – Functionality and Structure

Port E can be configured to perform one or more

of the following functions (see Figure 31, page 69):

MCU I/O Mode

In-System Programming (ISP) – JTAG port can

be enabled for programming/erase of the PSD

device. (See the section entitled “RESET”, on

page 34, for more information on JTAG

programming.)

Open Drain – pins can be configured in Open

Drain Mode

Battery Backup features

– PE6 can be configured for a battery input sup-

ply, Voltage Standby (VSTBY).

– PE7 can be configured as a Battery-on Indi-

cator (VBATON), indicating when VCC is less

than VBAT.

Latched Address output – Provide latched

address output.

Port F – Functionality and Structure

Port F can be configured to perform one or more

of the following functions:

MCU I/O Mode

CPLD Output – External Chip Select (ECS7-

ECS0) can be connected to Port F or Port C.

CPLD Input – direct input to the CPLD, no Input

Macrocells (IMC)

Latched Address output – Provide latched

address output as per Table 41, page 61.

Data Port – connected to D7-D0 when Port F is

configured as Data Port for a non-multiplexed

bus

Peripheral Mode

MCU RESET Mode – for 16-bit Motorola 683xx

and HC16 MCUs

Port G – Functionality and Structure

Port G can be configured to perform one or more

of the following functions:

MCU I/O Mode

Latched Address output – Provide latched

address output as per Table 41, page 61.

Open Drain – pins can be configured in Open

Drain Mode

Data Port – connected to D15-D8 when Port G

is configured as Data Port for a non-multiplexed

bus

MCU RESET Mode – for 16-bit Motorola 683xx

and HC16 MCUs

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