PSD4235G2V-10UI datasheet(71/100 Pages) STMICROELECTRONICS

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PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Automatic Power-down (APD) Unit and Power-down Mode

The APD Unit, shown in Figure 32, puts the PSD

into Power-down mode by monitoring the activity

of Address Strobe (ALE/AS, PD0). If the APD Unit

is enabled, as soon as activity on Address Strobe

(ALE/AS, PD0) stops, a four bit counter starts

counting. If Address Strobe (ALE/AS, PD0) re-

mains inactive for fifteen clock periods of CLKIN

(PD1), Power-down (PDN) goes High, and the

PSD enters Power-down mode, as discussed

next.

Power-down Mode

By default, if you enable the APD Unit, Power-

down mode is automatically enabled. The device

enters Power-down mode if Address Strobe (ALE/

AS, PD0) remains inactive for fifteen periods of

CLKIN (PD1).

The following should be kept in mind when the

PSD is in Power-down mode:

If Address Strobe (ALE/AS, PD0) starts pulsing

again, the PSD returns to normal operation. The

PSD also returns to normal operation if either

PSD Chip Select Input (CSI, PD2) is Low or the

Reset (RESET) input is High.

The MCU address/data bus is blocked from all

memory and PLDs.

Various signals can be blocked (prior to Power-

down mode) from entering the PLDs by setting

the appropriate bits in the Power Management

Mode Registers (PMMR). The blocked signals

include MCU control signals and the common

CLKIN (PD1). Note that blocking CLKIN (PD1)

from the PLDs does not block CLKIN (PD1)

from the APD Unit.

All PSD memories enter Standby Mode and are

drawing standby current. However, the PLDs

and I/O ports blocks do

not go into Standby

Mode because you do not want to have to wait

for the logic and I/O to “wake-up” before their

outputs can change. See Table 49, page 71 for

Power-down mode effects on PSD ports.

Typical Standby current is or the order of µA.

This standby current value assumes that there

are no transitions on any PLD input.

Table 48. Effect of Power-down Mode on Ports

Figure 32. APD Unit

Table 49. PSD Timing and Standby Current During Power-down Mode

Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.

2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.

Port Function

Pin Level

MCU I/O

No Change

PLD Out

No Change

Address Out

Undefined

Data Port

Tri-State

Peripheral I/O

Tri-State

Mode

PLD Propagation Delay

Memory Access

Time

Access Recovery Time to

Normal Access

Typical Standby

Current

Power-down

Normal tPD (Note

No Access

tLVDV

50 µA (Note 2)

APD EN

PMMR0 BIT 1=1

ALE

RESET

CSI

CLKIN

TRANSITION

DETECTION

EDGE

DETECT

APD

COUNTER

POWER DOWN

(PDN) Select

DISABLE BUS

INTERFACE

Secondary Flash

Memory Select

Primary Flash

Memory Select

SRAM Select

CLR

DISABLE Primary and Secondary

FLASH Memory and SRAM

PLD

AI04939

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