PSD4235G2V-10UI datasheet(17/100 Pages) STMICROELECTRONICS

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PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

In-System Programming (ISP)

Using the JTAG signals on Port E, the entire PSD

device (memory, logic, configuration) can be pro-

grammed or erased without the use of the MCU.

In-Application Programming (IAP)

The primary Flash memory can also be pro-

grammed, or re-programmed, in-system by the

MCU executing the programming algorithms out of

the secondary Flash memory, or SRAM. The sec-

ondary Flash memory can be programmed the

same way by executing out of the primary Flash

memory. Table 5, page 17 indicates which pro-

gramming methods can program different func-

tional blocks of the PSD.

Page Register

The 8-bit Page Register expands the address

range of the MCU by up to 256 times. The paged

address can be used as part of the address space

to access external memory and peripherals, or in-

ternal memory and I/O. The Page Register can

also be used to change the address mapping of

the Flash memory blocks into different memory

spaces for IAP.

Power Management Unit (PMU)

The Power Management Unit (PMU) gives the

user control of the power consumption on selected

functional blocks based on system requirements.

The PMU includes an Automatic Power-down

(APD) Unit that turns off device functions during

MCU inactivity. The APD Unit has a Power-down

mode that helps reduce power consumption.

The PSDalso has some bits that are configured at

run-time by the MCU to reduce power consump-

tion of the CPLD. The Turbo Bit in PMMR0 can be

reset to ’0’ and the CPLD latches its outputs and

goes to Standby Mode until the next transition on

its inputs.

Additionally, bits in PMMR2 can be set by the

MCU to block signals from entering the CPLD to

reduce power consumption. See the section enti-

tled “POWER MANAGEMENT” on page 70 for

more details.

Table 5. Methods of Programming Different Functional Blocks of the PSD

Functional Block

JTAG-ISP

Device Programmer

IAP

Primary Flash Memory

Yes

Secondary Flash memory

Yes

PLD Array (DPLD and CPLD)

Yes

PSD Configuration

Yes

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