PSD4235G2V-10UI datasheet(16/100 Pages) STMICROELECTRONICS

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

PSD ARCHITECTURAL OVERVIEW

PSD devices contain several major functional

blocks. Figure 4, page 15 shows the architecture

of the PSD device family. The functions of each

block are described briefly in the following sec-

tions. Many of the blocks perform multiple func-

tions and are user configurable.

Memory

Each of the memory blocks is briefly discussed in

the following paragraphs. A more detailed discus-

sion can be found in the section entitled “Memory

Blocks“ on page 25.

The 8Mbit primary Flash memory is the main

memory of the PSD. It is divided into 16 equally-

sized sectors that are individually selectable.

The 512Kbit secondary Flash memory is divided

into 4 sectors. Each sector is individually select-

able.

The 256Kbit SRAM is intended for use as a

scratch-pad memory or as an extension to the

MCU SRAM. If an external battery is connected to

the PSD’s Voltage Standby (VSTBY, PE6) signal,

data is retained in the event of power failure.

Each memory block can be located in a different

address space as defined by the user. The access

times for all memory types includes the address

latching and DPLD decoding time.

PLDs

The device contains two PLD blocks, the Decode

PLD (DPLD) and the Complex PLD (CPLD), as

shown in Table 2, page 12, each optimized for a

different function. The functional partitioning of the

PLDs reduces power consumption, optimizes

cost/performance, and eases design entry.

The DPLD is used to decode addresses and to

generate Sector Select signals for the PSD inter-

nal memory and registers. The DPLD has combi-

natorial outputs, while the CPLD can implement

more general user-defined logic functions. The

CPLD has 16 Output Macrocells (OMC) and 8

combinatorial outputs. The PSD also has 24 Input

Macrocells (IMC) that can be configured as inputs

to the PLDs. The PLDs receive their inputs from

the PLD Input Bus and are differentiated by their

output destinations, number of product terms, and

Macrocells.

The PLDs consume minimal power. The speed

and power consumption of the PLD is controlled

by the Turbo Bit in PMMR0 and other bits in

PMMR2. These registers are set by the MCU at

run-time. There is a slight penalty to PLD propaga-

tion time when not in the Turbo mode.

I/O Ports

The PSD has 52 I/O pins divided among seven

ports (Port A, B, C, D, E, F, and G). Each I/O pin

can be individually configured for different func-

tions. Ports can be configured as standard MCU I/

O ports, PLD I/O, or latched address outputs for

MCUs using multiplexed address/data buses.

The JTAG pins can be enabled on Port E for In-

System Programming (ISP).

MCU Bus Interface

The PSD easily interfaces with most 8-bit or 16-bit

MCUs, either with multiplexed or non-multiplexed

address/data buses. The device is configured to

respond to the MCU’s control pins, which are also

used as inputs to the PLDs.

ISP via JTAG Port

In-System Programming (ISP) can be performed

through the JTAG signals on Port E. This serial in-

terface allows complete programming of the entire

PSD MODULE device. A blank device can be

completely programmed. The JTAG signals (TMS,

TCK, TSTAT, TERR, TDI, TDO) can be multi-

plexed with other functions on Port E. Table 3 indi-

cates the JTAG pin assignments.

Table 3. PLD I/O

Table 4. JTAG Signals on Port E

Name

Inputs

Outputs

Product

Terms

Decode PLD (DPLD)

Complex PLD (CPLD)

150

Port E Pins

JTAG Signal

PE0

TMS

PE1

TCK

PE2

TDI

PE3

TDO

PE4

TSTAT

PE5

TERR

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