PSD4235G2V-10UI datasheet(19/100 Pages) STMICROELECTRONICS

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PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS

Table 6 shows the offset addresses to the PSD

registers relative to the CSIOP base address. The

CSIOP space is the 256 bytes of address that is al-

located by the user to the internal PSD registers.

Table 6 provides brief descriptions of the registers

in CSIOP space. The following sections give a

more detailed description.

Table 6. Register Address Offset

Note: 1. Other registers that are not part of the I/O ports.

Port

Other(1)

Description

Data In

Reads Port pin as input, MCU I/O input mode

Control

Selects mode between MCU I/O or Address

Out

Data Out

Stores data for output to Port pins, MCU I/O

output mode

Direction

Configures Port pin as input or output

Drive Select

Configures Port pins as either CMOS or

Open Drain

Input Macrocell

Reads Input Macrocells

Enable Out

Reads the status of the output enable to the I/

O Port driver

Output

Macrocells A

READ – reads output of Macrocells A

WRITE – loads Macrocell Flip-flops

Output

Macrocells B

READ – reads output of Macrocells B

WRITE – loads Macrocell Flip-flops

Mask

Macrocells A

Blocks writing to the Output Macrocells A

Mask

Macrocells B

Blocks writing to the Output Macrocells B

Flash Memory

Protection 1

Read only – Primary Flash Sector Protection

Flash Memory

Protection 2

Read only – Primary Flash Sector Protection

Flash Boot

Protection

Read only – PSD Security and Secondary

Flash memory Sector Protection

JTAG Enable

Enables JTAG Port

PMMR0

Power Management Register 0

PMMR2

Power Management Register 2

Page

Page Register

Places PSD memory areas in Program and/

or Data space on an individual basis.

Memory_ID0

Read only – SRAM and Primary memory size

Memory_ID1

Read only – Secondary memory type and

size

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