PSD4235G2V-10UI datasheet(70/100 Pages) STMICROELECTRONICS

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PSD4256G6V

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

POWER MANAGEMENT

The PSD device offers configurable power saving

options. These options may be used individually or

in combinations, as follows:

All memory blocks in a PSD (primary Flash

memory, secondary Flash memory, and SRAM)

are built with power management technology. In

addition to using special silicon design

methodology, power management technology

puts the memories into Standby Mode when

address/data inputs are not changing (zero DC

current). As soon as a transition occurs on an

input, the affected memory “wakes up”,

changes and latches its outputs, then goes back

to standby. The designer does

not have to do

anything special to achieve memory Standby

Mode when no inputs are changing—it happens

automatically.

The PLD sections can also achieve Standby

Mode when its inputs are not changing, as de-

scribed for the Power Management Mode Reg-

isters (PMMR), later.

The Automatic Power Down (APD) block allows

the PSD to reduce to standby current

automatically. The APD Unit also blocks MCU

address/data signals from reaching the

memories and PLDs. This feature is available

on all PSD devices. The APD Unit is described

in more detail in the section entitled “Automatic

Power-down (APD) Unit and Power-down

Mode”, on page 71.

Built in logic monitors the Address Strobe of the

MCU for activity. If there is no activity for a cer-

tain period (the MCU is asleep), the APD Unit

initiates Power-down mode (if enabled). Once in

Power-down mode, all address/data signals are

blocked from reaching the PSD memories and

PLDs, and the memories are deselected inter-

nally. This allows the memories and PLDs to re-

main in Standby Mode even if the address/data

signals are changing state externally (noise,

other devices on the MCU bus, etc.). Keep in

mind that any unblocked PLD input signals that

are changing states keeps the PLD out of

Standby Mode, but not the memories.

PSD Chip Select Input (CSI, PD2) can be used

to disable the internal memories, placing them

in Standby Mode even if inputs are changing.

This feature does not block any internal signals

or disable the PLDs. This is a good alternative

to using the APD Unit, especially if your MCU

has a chip select output. There is a slight

penalty in memory access time when PSD Chip

Select Input (CSI, PD2) makes its initial

transition from deselected to selected.

The Power Management Mode Registers

(PMMR) can be written by the MCU at run-time

to manage power. All PSD devices support

“blocking bits” in these registers that are set to

block designated signals from reaching both

PLDs. Current consumption of the PLDs is

directly related to the composite frequency of

the changes on their inputs (see Figure 35,

page 77).

Significant power savings can be achieved by

blocking signals that are not used in DPLD or

CPLD logic equations at run-time. PSDsoft cre-

ates a fuse map that automatically blocks the

low address byte (A7-A0) or the control signals

(CNTL0-CNTL2, ALE and WRITE-Enable High-

byte (WRH/DBE, PD3)) if none of these signals

are used in PLD logic equations.

PSD devices have a Turbo bit in PMMR0. This

bit can be set to turn the Turbo mode off (the de-

fault is with Turbo mode turned on). While Turbo

mode is off, the PLDs can achieve standby cur-

rent when no PLD inputs are changing (zero DC

current). Even when inputs do change, signifi-

cant power can be saved at lower frequencies

(AC current), compared to when Turbo mode is

on. When the Turbo mode is on, there is a sig-

nificant DC current component, and the AC

component is higher.

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