PSD4235G2V-10UI datasheet(23/100 Pages) STMICROELECTRONICS

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PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Table 23. PMMR0 Register

Note: The bits of this register are cleared to zero following power-up. Subsequent Reset (RESET) pulses do not clear the registers.

Bit Definitions:

APD Enable

0 = Automatic Power-down (APD) is disabled.

1 = Automatic Power-down (APD) is enabled.

PLD Turbo

0 = PLD Turbo is on.

1 = PLD Turbo is off, saving power.

PLD Array CLK

0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off.

1 = CLKIN to the PLD AND array is disconnected, saving power.

PLD MCells CLK

0 = CLKIN to the PLD Macrocells is connected.

1 = CLKIN to the PLD Macrocells is disconnected, saving power.

Table 24. PMMR2 Register

Note: For Bit 4, Bit 3, Bit 2: See Table 34, page 47 for the signals that are blocked on pins CNTL0-CNTL2.

Bit Definitions:

PLD Array Addr

0 = Address A7-A0 are connected to the PLD array.

1 = Address A7-A0 are blocked from the PLD array, saving power.

Note: In X A Mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4.

PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected.

1 = CNTL2 input to the PLD AND array is disconnected, saving power.

PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected.

1 = CNTL1 input to the PLD AND array is disconnected, saving power.

PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected.

1 = CNTL0 input to the PLD AND array is disconnected, saving power.

PLD Array ALE

0 = ALE input to the PLD AND array is connected.

1 = ALE input to the PLD AND array is disconnected, saving power.

PLD Array WRH

0 = WRH/DBE input to the PLD AND array is connected.

1 = WRH/DBE input to the PLD AND array is disconnected, saving power.

Table 25. VM Register

Note: On RESET, Bits 1-4 are loaded to configurations that are selected by the user in PSDsoft. Bit 0 and Bit 7 are always cleared on RESET.

Bit 0-4 are active only when the device is configured in 8051 Mode.

Bit Definitions:

SR_code

0 = PSEN cannot access SRAM in 80C51XA modes.

1 = PSEN can access SRAM in 80C51XA modes.

Boot_Code

0 = PSEN cannot access Secondary NVM in 80C51XA modes.

1 = PSEN can access Secondary NVM in 80C51XA modes.

FL_Code

0 = PSEN cannot access Primary Flash memory in 80C51XA modes.

1 = PSEN can access Primary Flash memory in 80C51XA modes.

Boot_data

0 = RD cannot access Secondary NVM in 80C51XA modes.

1 = RD can access Secondary NVM in 80C51XA modes.

FL_data

0 = RD cannot access Primary Flash memory in 80C51XA modes.

1 = RD can access Primary Flash memory in 80C51XA modes.

Peripheral mode

0 = Peripheral mode of Port F is disabled.

1 = Peripheral mode of Port F is enabled.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

not used

(set to 0)

not used

(set to 0)

PLD

MCells CLK

PLD

Array CLK

PLD

Turbo

not used

(set to 0)

APD

Enable

not used

(set to 0)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

not used

(set to 0)

PLD

Array WRH

PLD

Array ALE

PLD Array

CNTL2

PLD Array

CNTL1

PLD Array

CNTL0

not used

(set to 0)

PLD

Array Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Peripheral

mode

not used

(set to 0)

not used

(set to 0)

FL_data

Boot_data

FL_code

Boot_code

SR_code

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