PSD4235G2V-10UI datasheet(76/100 Pages) STMICROELECTRONICS

76 / 100 page

PSD4256G6V

76/100

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

The state of the PSD Reset (RESET) signal does

not interrupt (or prevent) JTAG operations if the

JTAG pins are dedicated by an NVM configuration

bit (via PSDsoft). However, Reset (RESET) will

prevent or interrupt JTAG operations if the JTAG

Enable Register (as shown in Table 21, page 22)

is used to enable the JTAG pins.

The PSD supports JTAG In-System-Programma-

bility (ISP) commands, but not Boundary Scan.

ST’s PSDsoft software tool and FlashLINK JTAG

programming cable implement the JTAG In-Sys-

tem-Programmability (ISP) commands.

JTAG Extensions

TSTAT and TERR are two JTAG extension signals

enabled by a JTAG command received over the

four standard JTAG pins (TMS, TCK, TDI, and

TDO). They are used to speed Program and Erase

cycles by indicating status on PSD pins instead of

having to scan the status out serially using the

standard JTAG channel. See Application Note

AN1153.

TERR indicates if an error has occurred when

erasing a sector or programming in Flash memory.

This signal goes Low (active) when an Error con-

dition occurs, and stays Low until a specific JTAG

command is executed or a Reset (RESET) pulse

is received after an “ISC_DISABLE” command.

TSTAT behaves the same as Ready/Busy (PE4)

described in the section entitled “Ready/Busy

(PE4)”, on page 26. TSTAT is High when the

PSD4256G6V device is in READ Mode (primary

Flash memory and secondary Flash memory con-

tents can be read). TSTAT is Low when Flash

memory Program or Erase cycles are in progress,

and also when data is being written to the second-

ary Flash memory.

TSTAT and TERR can be configured as open-

drain type signals with a JTAG command.

Note: The state of Reset (Reset) does not interrupt

(or prevent) JTAG operations if the JTAG signals

are dedicated by an NVM Configuration bit (via

PSDsoft). However, Reset (Reset) prevents or in-

terrupts JTAG operations if the JTAG Enable Reg-

ister (as shown in Table 21, page 22) is used to

enable the JTAG signals.

Security and Flash memory Protection

When the security bit is set, the device cannot be

read on a Device Programmer or through the

JTAG Port. When using the JTAG Port, only a Full

Chip Erase command is allowed.

All other Program, Erase and Verify commands

are blocked. Full Chip Erase returns the device to

a non-secured blank state. The Security Bit can be

set in PSDsoft.

All primary Flash memory and secondary Flash

memory sectors can individually be sector protect-

ed against erasure. The sector protect bits can be

set in PSDsoft.

Table 52. JTAG Port Signals

INITIAL DELIVERY STATE

When delivered from ST, the PSD device has all

bits in the memory and PLDs set to 1. The PSD

Configuration Register bits are set to 0. The code,

configuration, and PLD logic are loaded using the

programming procedure. Information for program-

ming the device is available directly from ST.

Please contact your local sales representative.

Port E Pin

JTAG Signals

Description

PE0

TMS

Mode Select

PE1

TCK

Clock

PE2

TDI

Serial Data In

PE3

TDO

Serial Data Out

PE4

TSTAT

Status

PE5

TERR

Error Flag

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