CYT4DNJBJS datasheet(203/209 Pages) INFINEON

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Datasheet

203

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Revision history change log

Rev. *I Section Updates

Section

Change Description

Current Spec (Rev. *H)

New Spec (Rev. *I)

Reason for change

1. Features List

Graphics: Scale/Rotate/Blend

Supported

Supported (on the fly)

Correction

1. Features List

Graphics: FPD-link/LVDS Output

Dual channel LVDS at 220 MHz (max)

Dual channel LVDS at 220 MHz pixel clock

(max)

Correction

1. Features List

Graphics: FPD-link/LVDS Output

Single channel LVDS at 110 MHz (max)

Single channel LVDS at 110 MHz pixel

clock (max)

Correction

1. Features List

Graphics: MIPI CSI-2 Input

4 lane MIPI CSI-2 at 220 MHz (max)

4 lane MIPI CSI-2 at 220 MHz pixel clock

(max)

Correction

1. Features List

Graphics: MIPI CSI-2 Input

2 lane MIPI CSI-2 at 110 MHz (max)

2 lane MIPI CSI-2 at 110 MHz pixel clock

(max)

Correction

1. Features List

System: Watchdog timer and

multi-counter watchdog timer

Supported

Supported (WDT + 3× MCWDT)

MCWDT#0 tied to CM0+, MCWDT#1 to

CM7_0, MCWDT#2 to CM7_1

Correction

3.3 Peripherals

Note [13]

13.Only pins with GPIO_ENH cells and when

slew rate control is enabled meets the I2C

minimum fall time requirement. See Table

11-1 for Pin list and corresponding of IO-cell

types.

13.See Table 26-10 'Serial Communi-

cation Block (SCB) specifications' for

supported IO-cells and I2C modes.

Correction

3.3 Peripherals

3.3.9 Ethernet MAC

The device also supports Audio-Video

Bridging (AVB). The MAC supports standard

6-byte programmable addresses.

The device also supports Audio-Video

Bridging (AVB). The MAC supports

standard 6-byte programmable

addresses. Module uses AXI interface for

DMA access.

Correction

3.5 I/Os

Note [17]

17.Refer to the family-specific Architecture

TRM for more information on the I/O config-

urations (002-25800, TRAVEO™ T2G

Automotive

MCU cluster 2D architecture technical

reference manual).

17.Refer to the device Architecture TRM

for more details on the I/O configuration.

Correction

3.5 I/Os

3.5.1.3 GPIO SMC (GPIO_SMC)

Provides significant drive strength

compared to GPIO_STD and GPIO_ENH

(supports 30-mA drive) and also has

support for I2C Fast Plus Mode.

Provides significant drive strength

compared to GPIO_STD and GPIO_ENH

(supports 30-mA drive).

Correction

6. Peripheral I/O

map

Table 6-1: CAN: Message RAM CAN0

Instance size: 0x3FFF

Instance size: 0x4000

Correction

6. Peripheral I/O

map

Table 6-1: CAN: Message RAM CAN1

Instance size: 0x3FFF

Instance size: 0x4000

Correction

11. Package pin list

and alternate

functions

Port 11 has the following additional

features:

• Ability to pass full-level analog signals to

the SAR without clipping to VDDD in cases

where VDDD < VDDA_ADC

• Lower noise, for the most sensitive sensors

(none)

Removed

11. Package pin list

and alternate

functions

Table 11-1

Package: I/O Type

327-BGA: I/O Type

Pin: I/O Type

Package: I/O Type

327-BGA: HCon#0

Pin: (none)

Correction

11. Package pin list

and alternate

functions

Table 11-1

(none)

Name: XRES_L

Pin: F18

Added

16. Trigger Multi-

plexer

Figure 16-1

Minor changed in the figure

Correction

16. Trigger Multi-

plexer

Figure 16-2

Added comments under the figure

Correction

23. Bus masters

ID No. 9: CPUSS_MS_ID_FAST0

Description: Master ID for Ethernet0

Description: Master ID for External AXI

Master 0 (Ethernet#0)

Correction

23. Bus masters

ID No. 10: CPUSS_MS_ID_FAST1

Description: Master ID for JPEG Decoder

Description: Master ID for External AXI

Master 1 (JPEG Decoder)

Correction

26. Electrical specifi-

cations

Note [52]

52.EnsureVDDIO_GPIO_2 ≥0.8 × VDDA_ADC

when SARMUX0 is enabled.

(none)

Removed

26. Electrical specifi-

cations

Table 26-10

I2C Interface-Standard-mode

HSIO_STDLN:

CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<4:0

> = 0b00010, CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0,

CFG_IN/VTRIP_SEL<0:0> = 0b0,

CFG/DRIVE_MODE<2:0> =0b100,

CFG_SLEW_EXT/SLEW<2:0> =0b000

HSIO_STDLN:

CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<

2:0> = 0b010, CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0,

CFG_IN/VTRIP_SEL<0:0> = 0b0,

CFG/DRIVE_MODE<2:0> =0b100,

CFG_SLEW_EXT/SLEW<2:0> =0b000

(Note: SID138 is not valid for

HSIO_STDLN)

Correction

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