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CYT4DNJBJS bảng dữ liệu(PDF) 207 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 207 Page - Infineon Technologies AG |
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207 / 209 page ![]() Datasheet 207 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Revision history change log SID328 LPECO startup time Details/Condi- tions Details/Conditions: Startup time to 90% of final frequency Details/Conditions: Startup time to 90% of final frequency. Time from oscillator enable (BACKUP_LPECO_CTL.LPECO_EN< 0:0>=0b1) to stable oscillation and sufficient amplitude (BACKUP_LPECO_STATUS.LPECO_ READY<0:0>=0b1 and BACKUP_LPECO_STATUS.LPECO_A MPDET_OK<0:0>=0b1). Updated description SID334 7.2-MHz ECO startup time Details/Condi- tions Details/Conditions: Startup time to 90% of final frequency Details/Conditions: Startup time to 90% of final frequency. Time from oscillator enable (CLK_ECO_- CONFIG.ECO_EN<0:0>=0b1) to stable oscillation and sufficient amplitude (CLK_ECO_STATUS.ECO_OK<0:0>=0 b1 and CLK_ECO_STATUS.ECO_READY<0:0 >=0b1). Updated description SID335 33-MHz ECO startup time[ Details/Condi- tions Details/Conditions: Startup time to 90% of final frequency Details/Conditions: Startup time to 90% of final frequency. Time from oscillator enable (CLK_ECO_- CONFIG.ECO_EN<0:0>=0b1) to stable oscillation and sufficient amplitude (CLK_ECO_STATUS.ECO_OK<0:0>=0 b1 and CLK_ECO_STATUS.ECO_READY<0:0 >=0b1). Updated description SID342D1 Long term jitter Details/Condi- tions Details/Conditions: For 125 ns Guaranteed by Design fVCO: 800 MHz (spreading is off) fIN: ECO fPFD: 4 MHz fOUT: 100 MHz to 400 MHz Details/Conditions: For 125 ns Guaranteed by Design fVCO: 800 MHz (Integer mode) fIN: ECO fPFD: 4 MHz fOUT: 100 MHz to 400 MHz Updated description SID343D1 Long term jitter Details/Condi- tions Details/Conditions: For 500 ns Guaranteed by Design fVCO: 800 MHz (spreading is off) fIN: ECO fPFD: 4 MHz fOUT: 100 MHz to 400 MHz Details/Conditions: For 500 ns Guaranteed by Design fVCO: 800 MHz (Integer mode) fIN: ECO fPFD: 4 MHz fOUT: 100 MHz to 400 MHz Updated description SID344D1 Long term jitter Details/Condi- tions Details/Conditions: For 1000 ns Guaranteed by Design fVCO: 800 MHz (spreading is off) fIN: ECO fPFD: 4 MHz fOUT: 100 MHz to 400 MHz Details/Conditions: For 1000 ns Guaranteed by Design fVCO: 800 MHz (Integer mode) fIN: ECO fPFD: 4 MHz fOUT: 100 MHz to 400 MHz Updated description SID345E1 Long term jitter Details/Condi- tions Details/Conditions: For 10000 ns Guaranteed by Design fVCO: 800 MHz (spreading is off) fIN: ECO fPFD: 4 MHz fOUT: 100 MHz to 400 MHz Details/Conditions: For 10000 ns Guaranteed by Design fVCO: 800 MHz (Integer mode) fIN: ECO fPFD: 4 MHz fOUT: 100 MHz to 400 MHz Updated description SID362 WCO start up time Details/Condi- tions Details/Conditions: (none) Details/Conditions: Time from oscil- lator enable (BACKUP_CTL.WCO_EN<0:0>=0b1) to stable oscillation and sufficient amplitude (BACKUP_STATUS.WCO_OK<0:0>=0 b1) Updated description SID1607C DQ[7:0] input setup time All (none) Parameter: tISU Description: DQ[7:0] input setup time Min: tCK/2 ns Typ: – Max: – Details/Conditions: Only valid in non-DLP mode 160 MHz ≤ fDLL ≤ 320 MHz 10 MHz ≤ fCK ≤ 80 MHz SMIF0_COREx_CTL2.CLKOUT_DIV = [0b01, 0b10, 0b11] (divide by 4, 8, 16) Reference CK edge: Fall (pos edge capture mode) Added spec Rev. *I Electrical Spec Updates (continued) Spec ID Description Changed Item Current Spec (Rev. *H) New Spec (Rev. *I) Reason for Change |
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