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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CYT4DNJBJS bảng dữ liệu(PDF) 28 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 28 Page - Infineon Technologies AG |
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28 / 209 page  Datasheet 28 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual CYT4DN clock diagram 7CYT4DN clock diagram Figure 7-1 CYT4DN clock diagram IMO ECO EXT_CLK WCO ILO0 ILO1 ECO Prescaler FLL RTC WDT MCWDT Predivider (1/2/4/8) CLK_ PATH0 CSV CLK_LF CLK_REF_HF LS CLK_BAK LEGEND 1: Active Domain DeepSleep Domain Hibernate Domain Serial Interface Clock CLK_HF0 CLK_ILO0 CLK_REF_HF CLK_ILO0 CLK_ILO0 CLK_LF VIDEOSS SOUND_0/1/2 Ethernet Event Generator CXPI SCB[*] SAR ADC CAN FD CLK_GR5 Divider (1-256) CM7_0 CM7_1 CLK_FAST_0 Divider (1-256) Divider (1-256) CLK_FAST_1 P-DMA / M-DMA Divider (1-256) CLK_MEM CPUSS Fast Infrastructure Divider (1-256) CLK_SLOW CM0+ CPUSS Slow Infrastructure CRYPTO PERI Divider (1-256) CLK_PERI TCPWM[0] IOSS CPUSS(DEBUG) Divider (1-256) CSV Reference Clock Monitored Clock LEGEND 2: Relationship of Monitored Clock and Reference Clock LIN Divider (1-256) CLK_GR6 SMIF_0/1 Peripheral Clock Dividers #0 Peripheral Clock Dividers #1 SCB[0] Divider (1-256) CLK_GR4 I2S External Clock Tx_CLK, Rx_CLK and REF_CLK to Ethernet PHY, TSU ROM/SRAM/ FLASH TCK/SWDCLK froma Debugger Divider (1-256) SRSS EFUSE Divider (1-256) CLK_GR9 Divider (1-256) CLK_TRC_DBG LEGEND 3: One Clock Line Multiple Clock Lines PCLK_CANFD[x]_CLOCK_CAN[y] PCLK_CXPI_CLOCK_CH_EN[x] PCLK_LIN_CLOCK_CH_EN[x] PCLK_SCB[x]_CLOCK PCLK_PASS_CLOCK_SAR[x] PCLK_SMARTIO[x]_CLOCK PCLK_TCPWM0_CLOCKS[x] PCLK_CPUSS_CLOCK_TRACE_IN LPECO LPECO Prescaler MUX MUX MUX MUX PLL#0 PLL400#0 Predivider (1/2/4/8) CLK_ PATH1 CLK_HF1 MUX MUX MUX PLL#1 PLL400#1 Predivider (1/2/4/8) CLK_ PATH2 MUX MUX MUX PLL#2 PLL400#2 Predivider (1/2/4/8) CLK_ PATH3 CLK_HF3 MUX MUX MUX CLK_HF2 PLL#3 PLL400#3 Predivider (1/2/4/8) CLK_ PATH4 CLK_HF4 MUX MUX MUX PLL#4 PLL400#4 Predivider (1/2/4/8) CLK_ PATH5 CLK_HF5 MUX MUX MUX PLL#5 PLL200#0 Predivider (1/2/4/8) CLK_ PATH6 MUX MUX MUX PLL#6 PLL200#1 Predivider (1/2/4/8) CLK_ PATH7 CLK_HF7 MUX MUX MUX CLK_HF6 PLL#7 PLL200#2 Predivider (1/2/4/8) CLK_ PATH8 CLK_HF8 MUX MUX MUX Predivider (1/2/4/8) CLK_HF9 MUX Predivider (1/2/4/8) MUX Predivider (1/2/4/8) CLK_HF11 MUX CLK_HF10 Predivider (1/2/4/8) CLK_HF12 MUX Predivider (1/2/4/8) CLK_HF13 MUX CLK_ PATH9 MUX MUX CSV CSV CSV CSV CSV CSV CSV CSV CSV CSV CSV CSV CSV MUX LS LS LS LS MUX LS LS CSV CSV CSV CLK_IF_SRSS0 CLK_IF_SRSS1 CLK_IF_SRSS2 CLK_GR3 CLK_GR8 CSV CLK_ILO0 |
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