CYT4DNJBJS datasheet(14/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.2.4.1

IMO clock source

The IMO is the frequency reference in CYT4DN when no external reference is available or enabled. The IMO

operates at a frequency of around 8 MHz.

3.2.4.2

ILO clock source

An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in

DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven

counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock

supervision.

3.2.4.3

PLL and FLL

A PLL (three 200 MHz and five 400 MHz) or FLL may be used to generate high-speed clocks from the IMO, ECO, or

an EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of 35 µs) in exchange for a small

amount (±2%) of frequency error[10] and a lower max output frequency (100 MHz instead of up to 400 MHz).

400-MHz PLLs supports spread spectrum clock generation (SSCG) with down spreading.

3.2.4.4

Clock supervisor

Each clock supervisor (CSV) allows one clock (reference) to supervise the behavior of another clock (monitored).

Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the

frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the

frequency range comparator detects a stopped clock or a clock outside the specified frequency range, an

abnormal state is signaled and either a reset or an interrupt is generated.

3.2.4.5

EXT_CLK

One of three GPIO_STD I/Os can be used to provide an external clock input of up to 100 MHz. This clock can be

used as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.

3.2.4.6

ECO

The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.

It supports fundamental mode (non-overtone) quartz crystals, in the range of 7.2 to 33.34 MHz. When used in

conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO

accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the

available I/O functions.

CLK_HF4

Ethernet Internal Clock

CLK_HF5

Sound Subsystem #0 (TDM, SG, PWM, MIXER, DAC), Ethernet TSU

CLK_HF6

Sound Subsystem #1 (TDM, SG, PWM, MIXER)

CLK_HF7

Sound Subsystem #2 (TDM, SG, PWM)

CLK_HF8

SMIF #0

CLK_HF9

SMIF #1

CLK_HF10

Video Subsystem

CLK_HF11

Video Display #0

CLK_HF12

Video Display #1

CLK_HF13

CSV

Table 3-1

CLK_HF destinations (continued)

Name

Description

Note

10.Operation of reference-timed peripherals (such as a UART) with an FLL-based reference is not recommended due to the allowed.

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