CYT4DNJBJS datasheet(15/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.2.4.7

LPECO

The LPECO provides high-frequency clocking using an external crystal connected to the LPECO_IN and

LPECO_OUT pins. It supports fundamental mode (non-overtone) quartz crystals, in the range of 3.99 to 8.01 MHz.

LPECO can operate during DeepSleep, and Hibernate modes with significant lower current consumptions. It can

also be used for real-time-clock applications. When used in conjunction with the PLL, it generates CPU and

peripheral clocks up to device’s maximum frequency.

3.2.4.8

WCO

The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external

32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock

reference for CLK_LF, which is the clock source for the MCWDT and RTC.

3.2.5

Reset

CYT4DN can be reset from a variety of sources, including software. Most reset events are asynchronous and

guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT,

software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and

allows software to determine the cause of the reset. An XRES_L pin is available for external reset.

3.2.6

Watchdog timer

CYT4DN has one watchdog timer (WDT) and three multi-counter watchdog timers (MCWDT).

The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from

Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT

timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause

An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are

only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used

separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.

3.2.7

Power modes

CYT4DN has six power modes that apply to the core functions, CM0+ core, and peripherals without power

switches. Power modes for the CM7 cores and VIDEOSS are controlled separately.

• Active – all peripherals are available

• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are

available, but with limited capability

• Sleep – all peripherals except the CPUs are available

• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are

available, but with limited capability

• DeepSleep – only peripherals which work with CLK_LF are available

• Hibernate – the device and I/O states are frozen, the device resets on wakeup

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