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CYT4DNJBJS bảng dữ liệu(PDF) 49 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 49 Page - Infineon Technologies AG |
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49 / 209 page ![]() Datasheet 49 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Interrupts and wake-up assignments 57 ioss_interrupts_gpio_act_17_IRQn Active HSIO_STD_LN Port Interrupt #17 Interrupt 58 ioss_interrupts_gpio_act_18_IRQn Active HSIO_STD_LN Port Interrupt #18 Interrupt 59 ioss_interrupts_gpio_act_19_IRQn Active HSIO_STD_LN Port Interrupt #19 Interrupt 60 ioss_interrupts_gpio_act_20_IRQn Active HSIO_STD_LN Port Interrupt #20 Interrupt 61 ioss_interrupts_gpio_act_21_IRQn Active HSIO_STD_LN Port Interrupt #21 Interrupt 63 ioss_interrupts_gpio_act_23_IRQn Active HSIO_ENH Port Interrupt #23 Interrupt 64 ioss_interrupts_gpio_act_24_IRQn Active HSIO_ENH_PDIFF Port Interrupt #24 Interrupt 65 ioss_interrupts_gpio_act_25_IRQn Active HSIO_ENH Port Interrupt #25 Interrupt 66 ioss_interrupts_gpio_act_26_IRQn Active HSIO_ENH Port Interrupt #26 Interrupt 67 ioss_interrupts_gpio_act_27_IRQn Active HSIO_ENH_PDIFF Port Interrupt #27 Interrupt 68 ioss_interrupts_gpio_act_28_IRQn Active HSIO_ENH Port Interrupt #28 Interrupt 69 ioss_interrupts_gpio_act_30_IRQn Active HSIO_STD Port Interrupt #30 Interrupt 70 cpuss_interrupt_crypto_IRQn Active Crypto Accelerator Interrupt 71 cpuss_interrupt_fm_IRQn Active FLASH Macro Interrupt 72 cpuss_interrupts_cm7_0_fp_IRQn Active CM7_0 Floating Point operation fault 73 cpuss_interrupts_cm7_1_fp_IRQn Active CM7_1 Floating Point operation fault 74 cpuss_interrupts_cm0_cti_0_IRQn Active CM0+ CTI (Cross Trigger Interface) #0 75 cpuss_interrupts_cm0_cti_1_IRQn Active CM0+ CTI #1 76 cpuss_interrupts_cm7_0_cti_0_IRQn Active CM7_0 CTI #0 77 cpuss_interrupts_cm7_0_cti_1_IRQn Active CM7_0 CTI #1 78 cpuss_interrupts_cm7_1_cti_0_IRQn Active CM7_1 CTI #0 79 cpuss_interrupts_cm7_1_cti_1_IRQn Active CM7_1 CTI #1 80 evtgen_0_interrupt_IRQn Active Event gen Active domain interrupt 81 smif_0_interrupt_IRQn Active SMIF #0 (QSPI) interrupt 82 smif_1_interrupt_IRQn Active SMIF #1 (QSPI) interrupt 83 eth_0_interrupt_eth_0_IRQn Active Ethernet #0 priority queue[0] 84 eth_0_interrupt_eth_1_IRQn Active Ethernet #0 priority queue[1] 85 eth_0_interrupt_eth_2_IRQn Active Ethernet #0 priority queue[2] 86 canfd_0_interrupt0_IRQn Active CAN0, Consolidated interrupt #0 for all channels 87 canfd_0_interrupt1_IRQn Active CAN0, Consolidated interrupt #1 for all channels 88 canfd_1_interrupt0_IRQn Active CAN1, Consolidated interrupt #0 for all channels 89 canfd_1_interrupt1_IRQn Active CAN1, Consolidated interrupt #1 for all channels 90 canfd_0_interrupts0_0_IRQn Active CAN0, Interrupt #0, Channel #0 91 canfd_0_interrupts0_1_IRQn Active CAN0, Interrupt #0, Channel #1 96 canfd_0_interrupts1_0_IRQn Active CAN0, Interrupt #1, Channel #0 97 canfd_0_interrupts1_1_IRQn Active CAN0, Interrupt #1, Channel #1 102 canfd_1_interrupts0_0_IRQn Active CAN1, Interrupt #0, Channel #0 103 canfd_1_interrupts0_1_IRQn Active CAN1, Interrupt #0, Channel #1 108 canfd_1_interrupts1_0_IRQn Active CAN1, Interrupt #1, Channel #0 109 canfd_1_interrupts1_1_IRQn Active CAN1, Interrupt #1, Channel #1 114 lin_0_interrupts_0_IRQn Active LIN0 Channel #0 Interrupt 115 lin_0_interrupts_1_IRQn Active LIN0 Channel #1 Interrupt 130 cxpi_0_interrupts_0_IRQn Active CXPI0 Channel #0 Interrupt Table 14-1 Peripheral interrupt assignments and wake-up sources (continued) Interrupt Source Power mode Description |
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