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CYT4DNJBJS bảng dữ liệu(PDF) 51 Page - Infineon Technologies AG

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Giải thích chi tiết về linh kiện  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
PDF  209 Pages
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nhà sản xuất  INFINEON [Infineon Technologies AG]
Trang chủ  http://www.infineon.com
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Datasheet
51
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
183
pass_0_interrupts_sar_23_IRQn
Active
SAR0, Logical Channel #23 Interrupt
184
pass_0_interrupts_sar_24_IRQn
Active
SAR0, Logical Channel #24 Interrupt
185
pass_0_interrupts_sar_25_IRQn
Active
SAR0, Logical Channel #25 Interrupt
186
pass_0_interrupts_sar_26_IRQn
Active
SAR0, Logical Channel #26 Interrupt
187
pass_0_interrupts_sar_27_IRQn
Active
SAR0, Logical Channel #27 Interrupt
188
pass_0_interrupts_sar_28_IRQn
Active
SAR0, Logical Channel #28 Interrupt
189
pass_0_interrupts_sar_29_IRQn
Active
SAR0, Logical Channel #29 Interrupt
190
pass_0_interrupts_sar_30_IRQn
Active
SAR0, Logical Channel #30 Interrupt
191
pass_0_interrupts_sar_31_IRQn
Active
SAR0, Logical Channel #31 Interrupt
280
axi_dmac_0_interrupts_0_IRQn
Active
CPUSS AXI M-DMA1, Channel #0 Interrupt
281
axi_dmac_0_interrupts_1_IRQn
Active
CPUSS AXI M-DMA1, Channel #1 Interrupt
282
axi_dmac_0_interrupts_2_IRQn
Active
CPUSS AXI M-DMA1, Channel #2 Interrupt
283
axi_dmac_0_interrupts_3_IRQn
Active
CPUSS AXI M-DMA1, Channel #3 Interrupt
288
cpuss_interrupts_dmac_0_IRQn
Active
CPUSS M-DMA0, Channel #0 Interrupt
289
cpuss_interrupts_dmac_1_IRQn
Active
CPUSS M-DMA0, Channel #1 Interrupt
290
cpuss_interrupts_dmac_2_IRQn
Active
CPUSS M-DMA0, Channel #2 Interrupt
291
cpuss_interrupts_dmac_3_IRQn
Active
CPUSS M-DMA0, Channel #3 Interrupt
292
cpuss_interrupts_dmac_4_IRQn
Active
CPUSS M-DMA0, Channel #4 Interrupt
293
cpuss_interrupts_dmac_5_IRQn
Active
CPUSS M-DMA0, Channel #5 Interrupt
294
cpuss_interrupts_dmac_6_IRQn
Active
CPUSS M-DMA0, Channel #6 Interrupt
295
cpuss_interrupts_dmac_7_IRQn
Active
CPUSS M-DMA0, Channel #7 Interrupt
296
cpuss_interrupts_dw0_0_IRQn
Active
CPUSS P-DMA0, Channel #0 Interrupt
297
cpuss_interrupts_dw0_1_IRQn
Active
CPUSS P-DMA0, Channel #1 Interrupt
298
cpuss_interrupts_dw0_2_IRQn
Active
CPUSS P-DMA0, Channel #2 Interrupt
299
cpuss_interrupts_dw0_3_IRQn
Active
CPUSS P-DMA0, Channel #3 Interrupt
300
cpuss_interrupts_dw0_4_IRQn
Active
CPUSS P-DMA0, Channel #4 Interrupt
301
cpuss_interrupts_dw0_5_IRQn
Active
CPUSS P-DMA0, Channel #5 Interrupt
302
cpuss_interrupts_dw0_6_IRQn
Active
CPUSS P-DMA0, Channel #6 Interrupt
303
cpuss_interrupts_dw0_7_IRQn
Active
CPUSS P-DMA0, Channel #7 Interrupt
304
cpuss_interrupts_dw0_8_IRQn
Active
CPUSS P-DMA0, Channel #8 Interrupt
305
cpuss_interrupts_dw0_9_IRQn
Active
CPUSS P-DMA0, Channel #9 Interrupt
306
cpuss_interrupts_dw0_10_IRQn
Active
CPUSS P-DMA0, Channel #10 Interrupt
307
cpuss_interrupts_dw0_11_IRQn
Active
CPUSS P-DMA0, Channel #11 Interrupt
308
cpuss_interrupts_dw0_12_IRQn
Active
CPUSS P-DMA0, Channel #12 Interrupt
309
cpuss_interrupts_dw0_13_IRQn
Active
CPUSS P-DMA0, Channel #13 Interrupt
310
cpuss_interrupts_dw0_14_IRQn
Active
CPUSS P-DMA0, Channel #14 Interrupt
311
cpuss_interrupts_dw0_15_IRQn
Active
CPUSS P-DMA0, Channel #15 Interrupt
312
cpuss_interrupts_dw0_16_IRQn
Active
CPUSS P-DMA0, Channel #16 Interrupt
313
cpuss_interrupts_dw0_17_IRQn
Active
CPUSS P-DMA0, Channel #17 Interrupt
314
cpuss_interrupts_dw0_18_IRQn
Active
CPUSS P-DMA0, Channel #18 Interrupt
315
cpuss_interrupts_dw0_19_IRQn
Active
CPUSS P-DMA0, Channel #19 Interrupt
316
cpuss_interrupts_dw0_20_IRQn
Active
CPUSS P-DMA0, Channel #20 Interrupt
317
cpuss_interrupts_dw0_21_IRQn
Active
CPUSS P-DMA0, Channel #21 Interrupt
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power
mode
Description



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