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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CYT4DNJBJS bảng dữ liệu(PDF) 25 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 25 Page - Infineon Technologies AG |
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25 / 209 page  Datasheet 25 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Peripheral I/O map 6Peripheral I/O map Table 6-1 CYT4DN peripheral I/O map Section Description Base address Instances Instance size Group Slave PERI Peripheral interconnect 0x4000 0000 0 0 Peripheral group (0, 1, 2, 3, 4, 5, 6, 8, 9, 10) 0x4000 4000 10 0x40 Peripheral trigger group 0x4000 8000 13 0x400 Peripheral 1:1 trigger group 0x4000 C000 8 0x400 PERI_MS Peripheral interconnect, master interface 0x4002 0000 0 1 PERI Programmable PPU 0x4002 0000 10[21] 0x40 PERI Fixed PPU 0x4002 0800 582 0x40 PERI_PCLK Peripheral Clock Groups 0x4004 0000 2 0x2000 0 2 Crypto Cryptography component 0x4010 0000 1 0 CPUSS CPU subsystem (CPUSS) 0x4020 0000 2 0 FAULT Fault structure subsystem 0x4021 0000 2 1 Fault structures 0x4021 0000 4 0x100 IPC Inter process communication 0x4022 0000 2 2 IPC structures 0x4022 0000 8 0x20 IPC interrupt structures 0x4022 1000 8 0x20 PROT Protection 0x4023 0000 2 3 Shared memory protection unit structures 0x4023 2000 16 0x40 Memory protection unit structures 0x4023 4000 16 0x400 FLASHC Flash controller 0x4024 0000 2 4 SRSS System Resources Subsystem Core Registers 0x4026 0000 2 5 Clock Supervision High Frequency 0x4026 1400 14 0x10 Clock Supervision Reference Frequency 0x4026 1710 1 Clock Supervision Low Frequency 0x4026 1720 1 Clock Supervision Internal Low Frequency 0x4026 1730 1 Clock PLL 400 MHz 0x4026 1900 5 0x10 Multi Counter WDT 0x4026 8000 3 0x100 Free Running WDT 0x4026 C000 1 BACKUP SRSS Backup Domain/RTC 0x4027 0000 2 6 Backup Register 0x4027 1000 4 0x04 Note 21.These programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the device specific TRM to know more about the configuration of these programmable PPUs. |
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