CYT4DNJBJS datasheet(11/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.1

CPU subsystem

3.1.1

CPU

The CYT4DN CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and two 32-bit Arm® Cortex®-M7

CPUs, each with MPU, single/double-precision FPU, and 16-KB data and instruction caches. This subsystem also

includes P-/M-DMA controllers, a cryptographic accelerator, 6336 KB of code-flash, 128 KB of work-flash, 640 KB

of SRAM, and 64 KB of ROM.

The Cortex®-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following

completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,

SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by

an inter-processor communication (IPC) mechanism using hardware semaphores.

Each Cortex®-M7 CPU has 64 KB of instruction and 64 KB of data TCM with programmable read wait states. Each

TCM is clocked by the associated Cortex®-M7 CPU clock.

3.1.2

DMA controllers

CYT4DN has three DMA controllers: P-DMA0 with 32 general purpose and 44 dedicated channels, P-DMA1 with 16

general purpose and 68 dedicated channels, M-DMA0 with eight channels, and AXI M-DMA1 with four channels.

P-DMA is used for peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for

a large number of channels. Each P-DMA controller uses a single data-transfer engine that is shared by the

associated channels. General purpose channels have a rich interconnect matrix including P-DMA cross triggering

which enables demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an

ADC channel) to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and

provides high memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine

for each channel. They support independent accesses to peripherals using the AHB multi-layer bus. AXI M-DMA

is used to provide access to AXI slaves like VRAM.

3.1.3

Flash

CYT4DN has 6336 KB (6080 KB with a 32-KB sector size, and 256 KB with an 8-KB sector size) of code-flash with an

additional work-flash of 128 KB (96 KB with a 2-KB sector size, and 32 KB with a 128-B sector size). Work-flash is

optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW)

operation so that flash may be updated while the CPU is active. Both the code-flash and work-flash areas support

dual-bank operation for over-the-air (OTA) programming.

3.1.4

SRAM

CYT4DN has 640 KB of SRAM with three independent controllers. SRAM0 provides DeepSleep retention in 32-KB

increments while SRAM1/2 are selectable between fully retained and not retained.

3.1.5

ROM

CYT4DN has 64 KB of ROM that contains boot and configuration routines. This ROM enables secure boot and

authentication of user flash to guarantee a secure system.

3.1.6

Cryptography accelerator for security

The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy

check, pseudo random number generation, true random number generation, Galois/counter mode, and a vector

unit to support asymmetric key cryptography such as RSA and ECC.

Depending on the part number, this block is either completely or partially available or not available at all. See

“Ordering information” on page 186 for more details.

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