CYT4DNJBJS datasheet(208/209 Pages) INFINEON

208 / 209 page

Datasheet

208

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Revision history change log

SID1608C

DQ[7:0] input hold time

All

(none)

Parameter: tIH

Description: DQ[7:0] input hold time

Min: 0 ns

Typ: –

Max: –

Details/Conditions: Only valid in

non-DLP mode

160 MHz ≤ fDLL ≤ 320 MHz

10 MHz ≤ fCK ≤ 80 MHz

SMIF0_COREx_CTL2.CLKOUT_DIV =

[0b01, 0b10, 0b11] (divide by 4, 8, 16)

Reference CK edge: Fall (pos edge

capture

mode)

Added spec

SID866A

Clock Cycle

Details/Condi-

tions

Details/Conditions: TTL_DSP1_-

CLOCK

BGA (CL = 15 pF,

CFG_OUT/DRIVE_SEL<1:0>

=0b01 for HSIO_STD)

Details/Conditions: TTL_DSP1_-

CLOCK,

CL = 15 pF

Updated

description

SID873A

Clock pulse width

Details/Condi-

tions

Details/Conditions: TTL_DSP1_-

CLOCK pulse width

BGA (CL = 15 pF,

CFG_OUT/DRIVE_SEL<1:0>

=0b01 for HSIO_STD)

Details/Conditions: TTL_DSP1_-

CLOCK pulse

width,

CL = 15 pF

Updated

description

SID868A

Data/Control output to TTL_DSP1_-

CLOCK time

Details/Condi-

tions

Details/Conditions: TTL_DSP1_-

DATA_A0[11-0]

TTL_DSP1_DATA_A1[11-0]

TTL_DSP1_CONTROL[11-0]

(TCON for FPD-Link)

BGA (CL = 15 pF,

CFG_OUT/DRIVE_SEL<1:0>

=0b01 for HSIO_STD)

Details/Conditions: TTL_DSP1_-

DATA_A0[11-0]

TTL_DSP1_DATA_A1[11-0]

TTL_DSP1_CONTROL[11-0]

(TCON for FPD-Link)

CL = 15 pF

Updated

description

SID869A

TTL_DSP1_CLOCK to Data/Control valid

time

Details/Condi-

tions

Details/Conditions: TTL_DSP1_-

DATA_A0[11-0]

TTL_DSP1_DATA_A1[11-0]

TTL_DSP1_CONTROL[11-0]

(TCON for FPD-Link)

BGA (CL = 15 pF,

CFG_OUT/DRIVE_SEL<1:0>

=0b01 for HSIO_STD)

Details/Conditions: TTL_DSP1_-

DATA_A0[11-0]

TTL_DSP1_DATA_A1[11-0]

TTL_DSP1_CONTROL[11-0]

(TCON for FPD-Link)

CL = 15 pF

Updated

description

SID903

Output Clock Frequency (110 MHz)

All

(none)

Parameter: fPX110

Description: Output Clock

Frequency (110 MHz)

Min: 103.7 MHz

Typ: 110 MHz

Max: 116.3 MHz

Details/Conditions: When trans-

mitting an alternating 0/1 bit pattern

Added spec

SID904

Output Clock Frequency (55 MHz)

All

(none)

Parameter: fPX55

Description: Output Clock

Frequency (55 MHz)

Min: 52.35 MHz

Typ: 55 MHz

Max: 57.65 MHz

Details/Conditions: When trans-

mitting an alternating 0/1 bit pattern

Added spec

SID905

Output Clock Frequency (28 MHz)

All

(none)

Parameter: fPX28

Description: Output Clock

Frequency (28 MHz)

Min: 26.66 MHz

Typ: 28 MHz

Max: 29.34 MHz

Details/Conditions: When trans-

mitting an alternating 0/1 bit pattern

Added spec

SID906

Output Clock Frequency (14 MHz)

All

(none)

Parameter: fPX14

Description: Output Clock

Frequency (14 MHz)

Min: 13.28 MHz

Typ: 14 MHz

Max: 14.72 MHz

Details/Conditions: When trans-

mitting an alternating 0/1 bit pattern

Added spec

SID907

Output Clock Frequency (7 MHz)

All

(none)

Parameter: fPX7

Description: Output Clock

Frequency (7 MHz)

Min: 6.59 MHz

Typ: 7 MHz

Max: 7.41 MHz

Details/Conditions: When trans-

mitting an alternating 0/1 bit pattern

Added spec

SID1449

Pixel clock frequency

All

(none)

Parameter: fPX_BGA

Description: Pixel clock frequency

Min: –

Typ: –

Max: 220 MHz

Added spec

Rev. *I Electrical Spec Updates (continued)

Spec ID

Description

Changed Item

Current Spec (Rev. *H)

New Spec (Rev. *I)

Reason for Change

CYT4DNJBJS bảng dữ liệu(PDF) 208 Page - Infineon Technologies AG

CYT4DNJBJS bảng dữ liệu(HTML) 208 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL