CYT4DNJBJS datasheet(200/209 Pages) INFINEON

tên linh kiện	CYT4DNJBJS

Giải thích chi tiết về linh kiện	TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual

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Datasheet

200

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Errata

13. Hardfault may occur when calling ReadSWPU or WriteSWPU while executing EraseSector or ProgramRow in non-blocking

mode

Problem Definition

ReadSWPU or WriteSWPU read data from bank#0 in SFlash. While doing that the check for active

non-blocking erase or program of bank#0 is not performed. Therefore, reading bank#0 while there is an

active erase/program operation will trigger a bus error which can result in a hardfault occurrence based on

FLASHC_FLASH_CTL register settings.

Parameters Affected

N/A

Trigger Condition(s)

Calling ReadSWPU or WriteSWPU while executing EraseSector or ProgramRow in non-blocking mode on

bank#0.

Scope of Impact

ReadSWPU or WriteSWPU can’t be used while executing EraseSector or ProgramRow in non-blocking mode

on bank#0.

Workaround

Do not use ReadSWPU or WriteSWPU while executing EraseSector or ProgramRow in non-blocking mode

on bank#0.

Fix Status

No silicon fix planned. TRM will be updated.

Impact on Infineon

Software

HSM-Perf-Lib: While executing EraseSector or ProgramRow in non-blocking mode on bank#0, users must

not call CySldProt_GetSwpuFlashStructCfg or, if CySldProt_SwpuFlashStructGroupConfigurations is

non-empty, CySldProt_VerifySecureDomainFlashWriteProtection.

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