CYT4DNJBJS datasheet(198/209 Pages) INFINEON

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Datasheet

198

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Errata

Fix Status

Will be fixed to update the Flash settings from the date code 312xxxxx, via Manufacturing Test Program

Update for Code Flash setting; this fix is transferred to TRAVEO™ T2G devices during Infineon Factory Test

Flow. Fixed devices will be identified by Device Date Code, which is marked on every TRAVEO™ T2G device.

7. Limitation for keeping the port state from peripheral IP after wakeup from DeepSleep

Problem Definition

The port state is not retained when the port selects peripheral IP (except for LIN or CAN FD) and MCU wakes

up from DeepSleep.

Parameters Affected

N/A

Trigger Condition(s)

The port selects peripherals (except for LIN or CAN-FD) and MCU wakes up from DeepSleep.

Scope of Impact

Unexpected port output change might affect user system.

Workaround

If the port selects peripherals (except for LIN or CAN FD), and the port output value needs to be maintained

after wakeup from DeepSleep, set HSIOM_PRTx_PORT_SEL.IOy_SEL = 0 (GPIO) before DeepSleep and set

the required output value in GPIO configuration registers. After wakeup, change HSIOM_PRTx-

_PORT_SEL.IOy_SEL back to the peripheral module as needed.

Fix Status

No silicon fix planned. TRM will be updated to add above workaround.

8. A part of the PWR_CTL2.BGREF_LPMODE description is lacked in the existing register TRM

Problem Definition

The following is lacked from the PWR_CTL2.BGREF_LPMODE description in the existing register TRM.

“This register will not set unless CLK_ILO0_CONFIG.ILO0_ENABLE==1. When changing back to continuous

operation, keep ILO0 enabled for at least 5 ILO0 cycles after clearing this bit to allow for internal synchro-

nization.”

Parameters Affected

N/A

Trigger Condition(s)

Using the PWR_CTL2.BGREF_LPMODE.

Scope of Impact

PWR_CTL2.BGREF_LPMODE may not be set or cleared.

Workaround

Use the PWR_CTL2.BGREF_LPMODE according to the following description.

“This register will not set unless CLK_ILO0_CONFIG.ILO0_ENABLE==1. When changing back to continuous

operation, keep ILO0 enabled for at least 5 ILO0 cycles after clearing this bit to allow for internal synchro-

nization.”

Fix Status

No silicon fix planned. Register TRM will be updated.

9. Limitation of clock configuration before entering DeepSleep mode

Problem Definition

DeepSleep should not be entered while any FLL/PLL is enabled and using ECO/LPECO as its

reference clock. Since the unstable ECO/LPECO clock after wakeup is outside the allowed

reference clock limits for FLL/PLL, there is possibility of failing the DeepSleep wakeup.

Parameters Affected

N/A

Trigger Condition(s)

DeepSleep transition while any FLL/PLL is enabled and using ECO/LPECO as its reference clock.

Scope of Impact

There is possibility of failing the DeepSleep wakeup.

Workaround

If any FLL/PLL is operating with the ECO/LPECO as its reference clock, change the clock to either

ECO/LPECO direct or IMO direct or IMO with FLL/PLL before entering DeepSleep.

Fix Status

No silicon fix planned. TRM will be updated to add above workaround.

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