CYT4DNJBJS datasheet(194/209 Pages) INFINEON

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Datasheet

194

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Errata

This section describes the errata for the CYT4DN product family. Details include errata trigger conditions, scope of impact, available

workaround, and silicon revision applicability. Contact your local Infineon Sales Representative if you have questions.

Part Numbers Affected

CYT4DN Qualification Status

Production samples

CYT4DN Errata Summary

The following table defines the errata applicability to available CYT4DN family devices.

Part Number

All CYT4DN parts

Items

Errata ID

CYT4DN

Silicon Rev.

Fix Status

[1.] CAN FD RX FIFO top pointer feature does not

function as expected

CYT4DNJBACQ1BZSGS

CYT4DNJBBCQ1BZSGS

CYT4DNJBCCQ1BZSGS

CYT4DNJBDCQ1BZSGS

CYT4DNJBECQ1BZSGS

CYT4DNJBFCQ1BZSGS

CYT4DNJBGCQ1BZSGS

CYT4DNJBHCQ1BZSGS

CYT4DNJBJCQ1BZSGS

CYT4DNJBKCQ1BZSGS

CYT4DNJBLCQ1BZSGS

CYT4DNJBMCQ1BZSGS

CYT4DNJBNCQ1BZSGS

CYT4DNJBPCQ1BZSGS

CYT4DNJBQCQ1BZSGS

CYT4DNJBRCQ1BZSGS

No silicon fix planned.

Use workaround.

[2] CAN FD debug message handling state machine

not get reset to Idle state when

CANFD_CH_CCCR.INIT is set

No silicon fix planned.

Use workaround.

[3] No YUV422 allowed in Direct Capture Mode

153

No silicon fix planned.

Use workaround.

[4] SWRESET register field of VIDEOSS0_TCONx_S-

WRESET violates the spec

172

No silicon fix planned.

Use workaround.

[5] Crypto ECC errors may be set after boot with

application authentication

185

No silicon fix planned.

TRM will be updated.

[6] Incomplete erase of Code Flash cells could

happen Erase Suspend / Erase Resume is used along

with Erase Sector operation in Non-Blocking mode

198

Will be fixed to update

the Flash settings, from

the date code 312xxxxx.

[7] Limitation for keeping the port state from

peripheral IP after wakeup from DeepSleep

199

No silicon fix planned.

TRM will be updated.

[8] A part of the PWR_CTL2.BGREF_LPMODE

description is lacked in the existing register TRM

201

No silicon fix planned.

updated.

[9] Limitation of clock configuration before entering

DeepSleep mode

202

No silicon fix planned.

TRM will be updated.

[10] Several data retention information in Register

TRM are incorrect

203

No silicon fix planned.

updated.

[11] SCBx_INTR_TX.UNDERFLOW bit may be set

unintentionally

204

No silicon fix planned.

updated.

[12] Conditions in datasheet for standard SMIF SDR

mode extended

205

No silicon fix planned.

Datasheet was updated

to add the new recom-

mended configuration

(SMIFx_CO-

REy_CTL2.TX_SDR_EX-

TRA_SETUP = 1).

[13] Hardfault may occur when calling ReadSWPU or

WriteSWPU while executing EraseSector or

ProgramRow in non-blocking mode

206

No silicon fix planned.

TRM will be updated.

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