CYT4DNJBJS datasheet(199/209 Pages) INFINEON

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Datasheet

199

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Errata

10. Several data retention information in Register TRM are incorrect

Problem Definition

The following registers are described as ‘Retained’ in the Register TRM while it is not guaranteed that the

value before entering DeepSleep mode is still readable from the register.

- SARADC: PASSx_SARy_CHz_RESULT

- SRSS: PWR_LVD_STATUS

- SRSS: PWR_LVD_STATUS2

- SRSS: CLK_CAL_CNT1

- SRSS: CLK_CAL_CNT2

- SRSS: CLK_FLL_STATUS

- SRSS: WDT_INTR

- SRSS: WDT_INTR_MASKED

- SRSS: CLK_PLL400Mx_STATUS

- MIXER: MIXER_DST_STRUCT_INTR_DST_MASKED

Parameters Affected

N/A

Trigger Condition(s)

Use of the related function and wakeup from DeepSleep mode.

Scope of Impact

The values before entering DeepSleep are not retained.

Workaround

For PASSx_SARy_CHz_RESULT, any of following:

1) Store the conversion values at another memory location before entering DeepSleep mode

2) Restart the conversion after wakeup from DeepSleep mode

For the other registers:

Rewrite the register value or read the status flags again after wakeup.

Fix Status

No silicon fix planned. Register TRM will be updated.

11. SCBx_INTR_TX.UNDERFLOW bit may be set unintentionally

Problem Definition

There is possibility of setting the SCBx_INTR_TX.UNDERFLOW bit even if the FIFO is not empty.

Parameters Affected

N/A

Trigger Condition(s)

Using the TX FIFO for SCB when the AHB-Lite interface clock (CLK_GR6) frequency of the AHB bus

is greater than 3x the SCB functionality clock (PCLK_SCBx_CLOCK).

Scope of Impact

SCBx_INTR_TX.UNDERFLOW bit may be set unintentionally.

Workaround

Ignore the SCBx_INTR_TX.UNDERFLOW bit if the FIFO is not empty.

Fix Status

No silicon fix planned. Register TRM will be updated.

12. Conditions in datasheet for standard SMIF SDR mode extended

Problem Definition

The required register setting for SMIF SDR mode

(SMIFx_COREy_CTL2.TX_SDR_EXTRA_SETUP = 1) was missing and could lead to incorrect

timing.

Parameters Affected

Recommended configuration for standard SMIF SDR mode got extended.

Trigger Condition(s)

Use of standard SMIF SDR mode.

Scope of Impact

Setup time (SID1605) might not be met in standard SMIF SDR mode.

Workaround

Follow the new recommended configuration (SMIFx_COREy_CTL2.TX_SDR_EXTRA_SETUP = 1).

Fix Status

No silicon fix planned. Datasheet was updated to add the new recommended configuration

(SMIFx_COREy_CTL2.TX_SDR_EXTRA_SETUP = 1).

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